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High−level Instructions
F106
(BSL)
P106
(PBSL)
Outline
Shifts one hexadecimal digit (4 bits) of the specified 16-bit data to the
left.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
"P106 (PBSL)" is not available.
Program example
Trigger
R0
10
F106 BSL, DT 0
D
Operands
Relay
Operand
Operand
WX WY WR
D
N/A
A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Shifts one hexadecimal digit (4 bits) in data register DT0 to the left when trigger R0 turns on.
The data in hexadecimal digit position 4 (bit positions 12 to 15) is shifted out and transferred to the lower digit
position (bit positions 0 to 3) of special data register DT9014 (with the FP0 T32, FP0R, FPΣ, FP−X, FP2,
FP2SH and FP10SH: DT90014).
Bit position
15
· · ·
Binary
1 0 0
DT0
Hexadecimal
Bit position
15
· ·
Binary
0
0 0
DT0
Hexadecimal
Bit position
15
· ·
Binary
0 0 0
DT9014/
Hexadecimal
DT90014
3 − 240
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Left shift of one hexadecimal digit (4 bits)
Ladder Diagram
Ladder Diagram
D
16-bit area to be shifted to the left
Timer/Counter
WL
SV
EV
(*1)
A
A
A
A
12
11
8
7
4
·
·
· ·
0
0 0 0
1
0 0 0
0
8
1
0
12
11
8
7
4
·
·
· ·
1
0
0 0
0
0
0 0
0
1
0
0
12
11
8
7
4
·
·
· ·
0
0 0 0
0
0 0 0
0
0
0
0
Index
Register
register
LD
FL
IX
DT
(*1)
(*2)
(*3)
(*4)
A
A
A
A
3
0
· ·
0 0 0
0
0
(H8100)
R0: on
3
0
· ·
0 0 0 0
0
(H1000)
3
0
· ·
1 0 0
0
8
(H8)
Boolean
Address
Instruction
10
ST
11
F106
DT
Constant
Index
Index
modifier
IY
K
H
A
N/A
N/A
A
A:
Available
N/A: Not Available
R
0
(BSL)
0
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