Philips DVDR1000/001 Service Manual page 305

Circuit-, IC Descriptions and List of Abbreviations
VSM_M_D(0-15)
VSM_M_LDQM
VSM_M_RASN
VSM_M_UDQM
VSM_M_WEN
VSM_UART_CTSN
1
VSM_UART_CTSN
2
VSM_UART_RTSN
1
VSM_UART_RTSN
2
VSM_UART_RX1
VSM_UART_RX2
VSM_UART_TX1
VSM_UART_TX2
Y_IN
Y_IN_7118
Y_OUT
YC(0-7)
9.12.2 Divio Board
+35V_DV_EDO
+3V3_DLY
+3V3_DV
+3V3_FPGAINT
+3V3_FPGAIO
+3V3_IEEE
+3V3_LINK
+3V3_PLL
+3V3_SRAM
+5V_PROC
+VCC_DV_RAM
1394_RSTN
A(0:8)
AUD_BCLK
AUD_MUTE
AUD_SDI
AUD_SDO
AUD_WS
BUFENN_AUD
BUFENN_VID
CEN
Versatile Stream Manager SDRAM
data bus
Versatile Stream Manager SDRAM
lower data mask enable
Versatile Stream Manager SDRAM
row address strobe
Versatile Stream Manager SDRAM
upper data mask enable
Versatile Stream Manager SDRAM
write enable
Versatile Stream Manager UART
clear to send to analog board
UART1
Versatile Stream Manager UART
clear to send to DVIO UART2
Versatile Stream Manager UART
ready to send to analog board
UART1
Versatile Stream Manager UART
ready to send to DVIO UART2
Versatile Stream Manager UART
received data to analog board
UART1
Versatile Stream Manager UART
received data to DVIO UART2
Versatile Stream Manager UART
transmitted data to analog board
UART1
Versatile Stream Manager UART
transmitted data to DVIO UART2
Luminance input from analog board
Luminance input to Video Input
Processor
Luminance output from Host
Decoder
Digital Video Bus for progressive
scan board
+3V3 Power supply EDO Bus
IC7404
+3V3 Power supply for IC7500
+3V3 Power supply for IC7404
+3V3 Internal Power supply for
IC7303
+3V3 Power supply for I/O pins of IC
7303
+3V3 Isolated Power supply for PHY
domain
+3V3 Power supply IC7103
+3V3 Power supply IC7307 &
IC7308
+3V3 Power supply IC7301, IC7302,
IC7305 & IC7306
+5V Power supply IC7200, IC7201,
IC7203 & IC7208
+3V3 Power supply for
DV_RAM(IC7400--> IC7404)
Reset of LINK IC(7103) and PHY
IC(7101)
Address lines
Audio Bit Clock
Audio Mute
Audio Serial Data Input
Audio Serial Data Output
Audio Word Select
Buffer Enable Audio
Buffer Enable Video
Control Enable
DVDR1000 /0x1 /691
CLK27M_CON 27MHz Clock to Digital Board
CLK27M_DV 27MHz Clock Digital Video Codec
CLK27M_OSC 27MHz Clock IC7304
CLOCKGENAUD Clock generator Audio
CLOCKGENVID Clock generator Video
CTSN Clear to Send
DATA Data from config ROM
DCLK Data Clock from config ROM
DV_ASN DVCODEC Address Strobe
DV_DRQN DVCODEC Data Request Interrupt
DV_DSLN DVCODEC Data Strobe Lower 8 bits
DV_DSUN DVCODEC Data Strobe Upper 8
Bits
DV_DTACKN DVCODEC Data Transfer
Acknowledge
DV_ERRN DVCODEC Error Interrupt
DV_HS_IN DVCODEC Horizontal
synchronisation In
DV_HS_OUT DVCODEC Horizontal
synchronisation Out
DV_LCN DVCODEC Last Code Interrupt
DV_PDN DVCODEC Power Down
DV_RSTN DVCODEC System Reset for
NW701
DV_RWN DVCODEC Read/Write control
signal
DV_VS DVCODEC Vertical synchronisation
FIFOA_A(0:15) FIFO buffer A Address bus
FIFOA_CEN(0:1) FIFO buffer A Chip enable
FIFOA_D(0:7) FIFO buffer A Data bus
FIFOA_OEN FIFO buffer A Output enable
FIFOA_WEN FIFO buffer A Write enable
FIFOB_A(0:15) FIFO buffer B Address bus
FIFOB_CEN(0:1) FIFO buffer B Chip enable
FIFOB_D(0:7) FIFO buffer B Data bus
FIFOB_OEN FIFO buffer B Output enable
FIFOB_WEN' FIFO buffer B Write enable
HAD(0:7) Host Address/Data bus for register
settings of IC7404
INIT_CONFN Initiate Configuration of IC7300
IO(0:30) Data bus of IC7404
ISPN In System Program Line(used for
programming IC7203)
LCASN Lower Column Address strobe for
IC7404 DRAMS
LINKFIFO_DQ(0:7) Audio/Video data
LINK_AVCLK LINK IC Audio/Video Interface Clock
LINK_AVERR0 LINK IC indicates an CRC error
LINK_AVERR1 LINK IC Audio/Video sequence error
LINK_AVFSYNC LINK IC Audio/Video frame sync
LINK_AVSYNC LINK IC Audio/Video packet sync
LINK_AVVALID LINK IC Audio/Video data valid
LINK_CSN LINK IC chip select
LINK_CYCLEOUT LINK IC Cycle clock
LINK_INTN LINK IC interrupt
OE Output enable
PA(0:15) SRAM processor address
PAD(0:7) SRAM processor data
PALE Processor Address Latch Enable
PHY_CNA PHY 1394 cable not active
PHY_LPS LINK IC power status
PINT0N Processor interrupt 0
PINT1N Processor interrupt 1
PORT1_1 Unused free port
PPSENN' Program store enable
PRDN Processor read
PRSTN Processor reset
PT0 Processor timer 0
PT1 Processor timer 1
PWRN Processor write
RASN Row address strobe
RESETN DVIO board reset
RTSN System Reset
RXD Receive Data
SRAMCE0N SRAM processor chip enable 0
9. GB 305