Philips DVDR1000/001 Service Manual page 226

GB 226 9. DVDR1000 /0x1 /691
GENERAL DESCRIPTION (continued)
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA selects the bank, A0-A10 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The 1 Meg x 16 SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architectures,
CKE
CLK
CONTROL
CS#
LOGIC
WE#
CAS#
RAS#
MODE REGISTER
12
REFRESH
ADDRESS
CONTROLLER
A0-A10, BA 12
REGISTER
REFRESH
COUNTER
11
Circuit-, IC Descriptions and List of Abbreviations
FUNCTIONAL BLOCK DIAGRAM
1 Meg x 16 SDRAM
ROW-
11 ADDRESS 11
LATCH
8
11
ROW-
ADDRESS
MUX
ROW-
11 ADDRESS 11
LATCH
but it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing the alternate bank
will hide the PRECHARGE cycles and provide seamless,
high-speed, random-access operation.
The 1 Meg x 16 SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between inter-
nal banks in order to hide precharge time, and the capability
to randomly change column addresses on each clock cycle
during a burst access.
BANK0
MEMORY
2,048
ARRAY
(2,048 x 256 x 16)
256 (x16)
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
256 16
COLUMN
8
DECODER
16
256
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
256 (x16)
BANK1
MEMORY
2,048
ARRAY
(2,048 x 256 x 16)
DQML,
DQMH
DATA
OUTPUT
REGISTER
DQ0-
16
DQ15
DATA
INPUT
8
REGISTER