Philips DVDR1000/001 Service Manual page 174

GB 174 9. DVDR1000 /0x1 /691
9.6.3 Functional Description
The DVIO module consists of the following blocks (see
blockdiagram):
1. IEEE1394 Interface
• PDI1394P11A (7101)
• PDI1394L21(7103)
2. Micro-controller
• 89C51RD(7203)
• 32kb RAM(7201)
3. FIFO and Control
• FPGA/EPLD(7308)
• SRAM(7301, 7302, 7305, 7306)
• Clock generation(7307, 7308)
– Independently tuneable audio and video clock,
implemented with FPGA and PLL
4. DV-Codec
• NW701(7404)
• DRAM(7402, 7403)
5. Audio & Video output
• Audio DAC UDA1334ATS(7602)
• Clock delay(7500)
• Tristate buffer(7505)
IEEE1394 Interface
The 1394 interface consists of a PDI1394P11A physical layer
and a PDI1394L21 link layer. The physical layer has its own
isolated power supply. It has the following features:
• S200 operation (200 megabit per second)
• One i.Link port (4 pin)
• 1nF isolation barrier between link and phy
• AV link port
• Isolated power supply for phy
Micro-Controller
The 89C51RD processor has a 8051 cpu with the following
extra features:
• 64 kilobyte of flash memory as program memory
• 1 kilobyte of internal data memory
• watchdog timer
• PCA outputs
• Power control modes
• Speed allowed up to 33 MHz but used at 22.1184 MHz
• On board ISP(In Circuit Programming) functionality
ISP
By use of In Circuit Programming, it is possible to update the
software of the DVIO board that is in the 89C51RD+. ISP can
be made active by resetting the processor and keeping the
ISPN pin low during reset. During ISP, the ISPN signal on the
board has to be kept low. This because the ISPN signal not
only drives the PSEN pin low, but will also put 12V instead of
5V on the VPP pin. When the ISP mode is active, the new
program can be sent to the microprocessor through the serial
port.
Fifo & Control
In decode mode, an isochronous AV-stream is flowing
through the IEEE1394 Interface into the FPGA. The FPGA
stores the data in a FIFO buffer (ping-pong buffer type, i.e. 2
buffers that can hold one whole frame each).
Reset
The FPGA controls the reset signals on the board. This has
the advantage that it is possible to reset the board both from
software and hardware.
Circuit-, IC Descriptions and List of Abbreviations
The board reset NRESET will reset the whole board, and the
software reset can reset everything except the
microprocessor itself. Power-on reset is implemented by
adding pull-ups and pull-downs to the reset inputs of the
devices. Since the FPGA will tri-state all the pins during
configuration, reset is active during configuration time. After
configuration of the FPGA, the reset signals are driven
inactive. The NRESET signal is used to reset the DVIO
board. After reset, the tri-state buffers to connector 1500 are
disabled.
Clock Circuit
There are 2 clocks to consider in the system, this is the video
clock and the audio clock. These two clocks do not have a
relation, so these clocks must be considered independently.
The video clock is approximately 27 MHz. When data is
flowing from an external source that is supposed to have the
same frequency, it does not have exactly the same clock.
Because of this, buffers may under-run of over-run. Since the
clock can not be directly recovered from the 1394 interface,
there has to be another solution. This solution is a tuneable
clock that is adjusted to the required frequency to process at
the rate of the incoming data.
The hardware implementation of such a tuneable clock is as
follows:
The same can be applied for the audio clock. For this clock,
a frequency of 8.192 MHz, 11.2896 MHz or 12.228 MHz is
required. This depends on the sample-rate of the audio
signal.
DV Codec
The AV-data will go from the FIFO to the NW701. The
NW701 decodes the stream into video data in 656 format and
audio data in I2S format.
The microprocessor has the ability to read the status
registers of the NW701 through the FPGA. By reading these
registers, extra data from the DV stream, that is not decoded
into audio or video, can be sent to the digital board using pin
TXD of the serial interface. This data includes time stamp
and some more.
SOFTWARE RESET
NRESET
FPGA
Figure 9-11
ClockGen
Raw clock
(CY2071)
(FPGA)
loopfilter
Figure 9-12
89C51RD+
PDI1394L21
NW701
CL 16532095_120.eps
150801
PLL
regular clock
slow-
CL 16532095_121.eps
150801