General Description - Philips DVDR1000/001 Service Manual

Circuit-, IC Descriptions and List of Abbreviations
9.9.2 IC7101; IC7306: SDRAM
SDRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2 and 3
• Industrial temperature range: -40°C to +85°C
OPTIONS
• Configuration
1 Meg x 16 (512K x 16 x 2 banks)
• Plastic Package - OCPL*
50-pin TSOP (400 mil)
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
• Refresh
2K or 4K with Self Refresh Mode at 64ms
• Operating Temperature
-40°C to +85°C
• Part Number Example: MT48LC1M16A1TG-7SIT
KEY TIMING PARAMETERS
SPEED CLOCK ACCESS TIME
CL = 3**
-6 166 MHz
-7 143 MHz
-8A 125 MHz
MT48LC1M16A1 SIT - 512K x 16 x 2 banks
MARKING
1M16A1
TG
-6
-7
-8A
S
I T
SETUP HOLD
5.5ns 2ns 1ns
5.5ns 2ns 1ns
6ns 2ns 1ns
DVDR1000 /0x1 /691
PIN ASSIGNMENT (Top View)
50-Pin TSOP
1
V
DD
DQ0 2
DQ1 3
4
VssQ
DQ2 5
6
DQ3
V Q 7
DD
DQ4 8
9
DQ5
VssQ 10
11
DQ6
DQ7 12
V Q 13
DD
14
DQML
WE# 15
16
CAS#
RAS# 17
CS# 18
19
BA
A10 20
21
A0
A1 22
A2 23
24
A3
V 25
DD
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16Mb (x16) SDRAM PART NUMBER
PART NUMBER
MT48LC1M16A1TG SIT

GENERAL DESCRIPTION

The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a dual 512K x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K x
16-bit banks is organized as 2,048 rows by 256 columns by
16 bits. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
9. GB 225
50
Vss
49 DQ15
48 DQ14
47 VssQ
46 DQ13
45
DQ12
44 V Q
DD
43 DQ11
42
DQ10
41 VssQ
40
DQ9
39 DQ8
38
V Q
DD
37
NC
36 DQMH
35
CLK
34 CKE
33
NC
32
A9
31 A8
30
A7
29 A6
28
A5
27
A4
26 Vss
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
ARCHITECTURE
1 Meg x 16