Philips DVDR1000/001 Service Manual page 238

GB 238 9. DVDR1000 /0x1 /691
STi5505 (Rev. Ax)
III - FUNCTIONAL DESCRIPTION
III.1 - Functional Modules
Figure 1 shows the subsystem modules that make
up the STi5505. These modules are outlined below.
III.1 - CPU
The Central Processing Unit (CPU) on the STi5505
is the ST20-C2 32-bit processor core. It contains
instruction processing logic, instruction and data
pointers and an operand register. It directly ac-
cesses the high speed on-chip SRAM memory,
which can store data or programs, and uses the
Caches to reduce access time to off chip program
and data memory.
The processor can access memory via the general
purpose External Memory Interface (EMI) or via the
SDRAM EMI which is shared with the MPEG de-
coder.
III.2 - Memory Subsystem
The STi5505 on-chip SRAM memory system provides
160 Mbytes/s internal data bandwidth, supporting pipe-
lined 2 cycles internal memory access at 25ns cycle
times. The STi5505 memory system consists of 2
Kbytes of SRAM, 2Kbytes of instruction cache, a
2Kbytes data cache that can be programmed to be
SRAM, and an external memory interface (EMI).
The STi5505 product has 2 Kbytes of on-chip
SRAM. The advantage of this is the ability t o store
time critical code on chip, for instance interrupt
routines, software kernels or device drivers, and
even frequently used data without these being
flushed from the caches.
The instruction and data caches are direct mapped with
a write-back system for the data cache and support
burst accesses to the external memories for refill and
write-back which are effective for increasing perform-
ance with page-mode and SDRAM memories.
The STi5505 EMI controls access to the external
memory and peripherals while the SDRAM EMI
provides access to the SDRAM buffer for the
MPEG decoders, ST20 and DMA peripherals.
The STi5505 EMI can access a 16 Mbytes (or
greater if DRAM is used) physical address space
in each of the four general purpose memory banks,
and provides sustained transfer rates of up to 80
Mbytes/s. Peripherals that support an asynchro-
nous data acknowledge are supported as is an
external Power PC which can share the bus with
the STi5505 and access the SDRAM buffer through
the device.
Circuit-, IC Descriptions and List of Abbreviations
High memory bandwidths up to 200 Mbytes/s can
be supported by the SDRAM EMI.
The STi5505 internal memory interconnect pro-
vides buffering and arbitration of memory access
requests to sustain very high throughput of memory
accesses.
III.3 - Syste m Services Module
The STi5505 system services module includes :
- Phase locked loop (PLL) - accepts 27MHz input
and generates all the internal high frequency
clocks needed for the CPU and the OS-Link.
- test access port - JTAG compatible.
- Diagnostics controller accessed via the JTAG
port providing :
- Bootstrapping during development
- Hardware breakpoint and watchpoint
- Real time trace
- External LSA triggering support.
III.4 - Serial Communications
To facilitate the connection of this system the front
end device and other peripherals, two UARTs
(ASCs) are included in the device. The UARTs
provide an asynchronous serial interface.
The UART can be programmed to support a range
of baud rates and data formats, for example, data
size, stop bits and parity. Two synchronous serial
communications (SSC) interfaces are provided on
the device. These can be used for a remote control
device for example via an I
III.5 - Interrupt Subsystem
The STi5505 interrupt subsystem supports eight
prioritized interrupt levels. Two external interrupt
pins are provided. Level assignment logic allows
any of the internal or external interrupts to be
assigned and, if necessary, share any interrupt
level.
III.6 - Front End Interf ace & DVD Decryption
The front end interface accepts sectors in the case
of DVD, MPEG-1 system stream in the case of VCD
and PCM data for CD-DA applications on an I2S
interface. In the case of VCD and CD-DA disks the
subcode information is input via a simple asynchro-
nous serial interface similar to a UART.
The bitstream and subcode stream then pass
through a "sector processor" block which handles
sector filtering in the case of DVD and sectorizing
using the subcode stream for VCD and CD-DA
systems.
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C or SPI bus.