General Description - Philips SACD 1000/001 Service Manual

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Circuit-, IC descriptions and list of abbreviations
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2 and 3
OPTIONS
• Configuration
1 Meg x 16 (512K x 16 x 2 banks)
• Plastic Package - OCPL*
50-pin TSOP (400 mil)
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
• Refresh
2K or 4K with Self Refresh Mode at 64ms
• Part Number Example: MT48LC1M16A1TG-7S
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
CL = 3**
-6
166 MHz
5.5ns
-7
143 MHz
5.5ns
-8A
125 MHz
*Off-center parting line
**CL = CAS (READ) latency
MARKING
1M16A1
TG
-6
-7
-8A
S
SETUP
HOLD
2ns
1ns
2ns
1ns
6ns
2ns
1ns
SACD 1000
MT48LC1M16A1 S - 512K x 16 x 2 banks
PIN ASSIGNMENT (Top View)
50-Pin TSOP
1
V
DD
2
DQ0
3
DQ1
4
VssQ
5
DQ2
6
DQ3
7
V
Q
DD
8
DQ4
9
DQ5
10
VssQ
11
DQ6
12
DQ7
13
V
Q
DD
14
DQML
15
WE#
16
CAS#
17
RAS#
18
CS#
19
BA
20
A10
21
A0
22
A1
23
A2
24
A3
25
V
DD
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16Mb (x16) SDRAM PART NUMBER
PART NUMBER
ARCHITECTURE
MT48LC1M16A1TG S
1 Meg x 16

GENERAL DESCRIPTION

The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a dual 512K x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K x
16-bit banks is organized as 2,048 rows by 256 columns by
16 bits. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
9.
GB 127
50
Vss
49
DQ15
48
DQ14
47
VssQ
46
DQ13
45
DQ12
44
V
Q
DD
43
DQ11
42
DQ10
41
VssQ
40
DQ9
39
DQ8
38
V
Q
DD
37
NC
36
DQMH
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
Vss
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0 A10)
2 (BA)
256 (A0 A7)

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