Philips SACD 1000/001 Service Manual page 77

Circuit-, IC descriptions and list of abbreviations
DSP for CD and DVD-ROM systems
FUNCTIONAL DESCRIPTION
Analog front-end
This block converts the HF input to the digital domain using
an 8-bit ADC proceeded by an AGC circuit to obtain the
optimum performance from the convertor. This block is
clocked by ADCCLK which is set by the external crystal
frequency plus a flexible clock multiplier and divider block.
PLL and bit detector
This subsystem recovers the data from the channel
stream. The block corrects asymmetry, performs noise
filtering and equalisation and finally recovers the bit clock
and data from the channel using a digital PLL.
The equalizer and the data slicer are programmable.
Digital logic
All the digital system logic is clocked from the master ADC
clock (ADCCLK) described above.
Advanced bit detector
The advanced bit detector offers improved data recovery
for multi-layer discs and contains two extra detection
circuits to increase the margins in the bit recovery block:
1. Adaptive slicer: adds a second stage slicer with higher
bandwidth
2. Run length 2 push-back: all T2 run lengths are pushed
back to T3, thereby automatically determining the
erroneous edge and shifting the transitions on that
edge.
Demodulator
F CD
RAME SYNC PROTECTION MODE
This circuit detects the frame synchronization signals.
Two synchronization counters are used in the SAA7335:
SACD 1000
1. The coincidence counter: this is used to detect the
coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 588 ±1 EFM clocks
apart.
2. The main counter: this is used to partition the EFM
signal into 17-bit words. This counter is reset when:
a) A sync coincidence is generated
b) A sync is found within ±6 EFM clocks of its
expected position.
The sync coincidence signal is also used to generate the
lock signal which will go active HIGH when 1 sync
coincidence is found. It will reset to LOW when, during
61 consecutive frames, no sync coincidence is found.
F DVD
RAME SYNC PROTECTION MODE
This circuit detects the frame synchronization signals.
Two synchronization counters are used in the SAA7335:
1. The coincidence counter: this is used to detect the
coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 1488 ±3 EFM+
clocks apart.
2. The main counter: this is used to partition the EFM+
signal into 16-bit words. This counter is reset when:
a) A sync coincidence is generated
b) A sync is found within ±10 EFM+ clocks of its
expected position.
The sync coincidence signal is also used to generate the
lock signal which will go active HIGH when 1 sync
coincidence is found. It will reset to LOW when, during
61 consecutive frames, no sync coincidence is found.
EFM/EFM+ demodulation
The 14-bit EFM (16-bit EFM+) data and subcode words
are decoded into 8-bit symbols.
9. GB 121
SAA7335