Fluke PM3082 Service Manual page 63

5.1 -8
DLENO-HT (Data Latch ENable) and DLEN1-HT determine if D9001 or D9002 reacts on the
SDA/SCL signals. The figure below indicates the relation between SDA and SCL.
/
SDA
/
SCL
DATA LINE
DATA VALID
Figure 5.12 Relation of serial bus signals SDA and SCL
D9003 and D9004 have outputs that control a number of on/off functions in the preamplifier. The IC's
are connected in cascade as a shift register. The IC's are controlled by the microprocessor on unit
A3. This happens via the data signal SDA (Serial DAta) and the synchronization signal SCL (Serial
CLock). The enable signal STROBEO-HT in relation with SCL and SDA is indicated in the figure
below. New data can be clocked into the shift register if STROBEO-HT is low. The new data becomes
available at the outputs at the low-to-high transition of STROBEO-HT.
CONFIGURATION OF HEF 4094 BUS
INPUT PULSES FOR HEF 4094 BUS:
DATA IS CLOCKED INTO THE HEF 4094 1C
AT POSITIVE SLOPE OF CLOCKPULSE:
STROBE-HT
OUTPUTS
Figure 5.13 Configuration of serial control bus
N9001, N9002 and N9003 are octal digital-to-analog converters (DAC's). Each IC has 8 outputs
capable of delivering a DC voltage that is adjustable between 0.5 and 9.5 V. This is controlled by the
microprocessor on unit A3 via 6 bits of information that allow 64 adjustment steps. This happens via
the data signal SDA (Serial DAta) and the synchronization signal SCL (Serial CLock). The data bits
are preceeded by address bits that are compared with the fixed address A0/A1/A2 applied to pin 7,
8 and 9. This determines if N9001, N9002 or N9003 reacts on the bitstream.
Note: a solder pad is present in the SDA and SCL input lines of every IC. This gives the possibility
to isolate a suspected IC from the other in case a fault is suspected.
\
V
CHANGE !
STABLE: OF DATA •
ALLOWED!
8 PARALLEL
OUTPUTS
\
!
!
8 PARALLEL
OUTPUTS
OLD DATA ^ NEW~D/ DATA
UNIT DESCRIPTIONS