Cpu Configuration - Supermicro SUPERSERVER User Manual

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UPER ERVER 7048R-C1RT/7048R-C1R User's Manual

CPU Configuration


This submenu displays the following CPU information as detected by the BIOS. It
also allows the user to configure CPU settings.
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Processor Socket
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Processor ID
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Processor Frequency
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Processor Max Ratio
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Processor Min Ratio
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Microcode Revision
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L1 Cache RAM
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L2 Cache RAM
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L3 Cache RAM
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CPU 1 Version
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CPU 2 Version
Clock Spread Spectrum
Select Enabled to allow the BIOS to monitor and attempt to reduce the level of
Electromagnetic Interference caused by the components whenever needed. The
options are Disabled and Enabled.
Hyper-Threading (All)
Select Enable to support Intel's Hyper-threading Technology to enhance CPU per-
formance. The options are Enable and Disable.
Cores Enabled
This feature allows the user to determine the number of CPU cores to enable.
Enter "0" to enable all cores. The default setting is 0, which enables all CPU cores
in the system.
Execute Disable Bit (Available if supported by the OS & the CPU)
Select Enable for Execute Disable Bit Technology support, which will allow the
processor to designate areas in the system memory where an application code
can execute and where it cannot, thus preventing a worm or a virus from flooding
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illegal codes to overwhelm the processor to damage the system during an attack.
The options are Enable and Disable. (Refer to Intel's and Microsoft's websites for
more information.)
PPIN Control
Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN)
control in the system. The options are Unlock/Enable and Unlock/Disable.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-
tions from the main memory to the L2 cache to improve CPU performance. The
options are Disable and Enable.
Adjacent Cache Prefetch (Available when supported by the CPU)
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.
Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options
are Disable and Enable.
Note: Please reboot the system for changes on this setting to take effect.
Please refer to Intel's website for detailed information.
DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)
If set to Enable, the DCU Streamer prefetcher will prefetch data streams from the
cache memory to the DCU (Data Cache Unit) to speed up data accessing and
processing to enhance CPU performance. The options are Disable and Enable.
DCU IP Prefetcher
If set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will prefetch IP
addresses to improve network connectivity and system performance. The options
are Enable and Disable.
Direct Cache Access (DCA)
Select Enable to use Intel DCA (Direct Cache Access) Technology to improve the
efficiency of data transferring and accessing. The options are Auto, Enable, and
Disable.
X2 APIC (Advanced Programmable Interrupt Controller)
Based on Intel's Hyper-Threading architecture, each logical processor (thread) is
assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-
able, the APIC ID will expand(X2) from 8 bits to 16 bits to provide 512 APIDs to each
thread for CPU performance enhancement. The options are Disable and Enable.
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Chapter 7: BIOS