Panasonic BT-M1950Y Service Manual page 100

Dl•MHIOUJ
2-2 Block diagram description
1 ) Command and data inputs
The input commands and display data are supplied by 8 bit serial transfer. The commands are decoded and the
control registers are set.
2) VRAM (display memory) write address count
VRAM write address control. Addresses can be set by the write address setting command. Automatic increment
during character code write to the VRAM.
Write address count is in the range of
O - 23
horizontal columns by
O - 11
vertical lines. Column
23
is followed by
column
O;
line
11
is followed by line
o.
3) Vertical display position control
The -H sync signal is counted from -V sync. The vertical display start position and VRAM read line address are
controlled.
4) Horizontal display position control
The dot clock from the -H sync rising edge is counted. The horizontal display start position and VRAM read column
address are controlled.
5) VRAM access control
VRAM read/write control. During write, used as the VRAM address for writing from the write address block. During
read, the address from the horizontal and vertical control blocks is used.
Since write to VRAM needs to be synchronized to the display operation in order to avoid disrupting the displayed
picture, the dot clock is used for timing adjustment during write. The dot clock oscillation is stopped and write to
VRAM is not performed during the horizontal sync period or at the dot clock stop command. Consequently, writing
interrupted by dot clock stoppage, or a write request during dot clock stoppage, is performed after restarting the dot
clock oscillation.
However, if an unexecuted write request is present, other write requests are not recognized until processing is
complete. Therefore, even if multiple write requests are produced during dot clock stoppage, only the first of these is
recognized.
6) VRAM
The video random access memory stores 11 bit display data. The data storage capacity is 24 characters x 12 lines
(288 characters).
7) Character generator ROM (CGROM)
The read only memory stores 128 types of character patterns. The CGROM is read by the VRAM output character
code and scan counter.
8) Screen display and CGROM access control
Screen display selection, such as character display on/off, edging, background, etc., and data read from the CGROM
are controlled.
9) Dot clock generator
The reference clock (dot clock) signal is generated during character display. An LC oscillator circuit is connected
externally. Since the dot clock phase needs to be synchronized to the video signal phase, oscillation stop/restart is
controlled by the horizontal sync signal (-H sync). The oscillation can also be stopped by the oscillation control
command.
Although an external clock can be input directly, as shown in Fig. 2-1, at least three clock cycles must also be input after
the -H sync falling edge.
-H SYNC
EXD
Fig. 2-1
10) Sync control
The phases of externally supplied horizontal and verti~al sync signal inputs are matched to signals synchronized to
internal circuits.
11) Blink period counter
The 6 bit counter counts the vertical sync signal (-V sync) for counting the blink period. The blink period is
approximately one second (-V sync x 64) and the blink ratio can be selected for 1:1, 1:3 or 3:1.
-100-