Integra DTR-7.6 Service Manual page 96

IC BLOCK DIAGRAMS AND DESCRIPTIONS
CS494003(Audio Decoder DSP)
PIN NO.
TERMINAL NAME/DESCRIPTION
1
UHS0, GPIO18 :DSPC control mode select Bit 0, General Purpose I/O
2
UHS1, GPIO19 :DSPC control mode select Bit 1, General Purpose I/O
3
INTREQ:Control Port Interrupt Request
4
FA1, FSCDIN :Host parallel address bit zero or SPI rerial control data input
5
GPIO20:General Purpose I/O can be individually configured and controlled by DSPC.
6
:Host Parallel Address Bit Zero or Serial Control Port Clock
FAO, FSCCLK
7
FHS2, FSCDIO, FSCDOUT:Mode select bit 2 or serial control port data input and output,parallel porttype select
8
GPIO21:General Purpose I/O can be individually configured and controlled by DSPC.
9
FDAT7:DSPAB Bidirectional Data Bus input
10
VDD6:2.5V supply voltage.
11
VSS6:2.5V ground.
12
FHS0, FWR, FDS:Mode select bit 0 or host write strobe or host data strobe
13
FHS1, FRD, FR/W:Mode select bit 1 or host parallel output enable or host parallel R/W
14
FDAT6:DSPAB Bidirectional Data Bus input
15
FCS:Host parallel chip select,Host serial SPI chip select
16
FINTREQ:Control port interrupt request
17
FDBCK:Reversed input:This pin is reversed and is pulled up with an external resistor.
18
FDAT5:DSPAB Bidirectional Data Bus input
19
FDAT4:DSPAB Bidirectional Data Bus input
20
VDD7:2.5V supply voltage.
21
VSS7:2.5V ground.
22
FDAT3:DSPAB Bidirectional Data Bus input
23
FDBDAReversed input:This pin is reversed and is pulled up with an external resistor.
24
FDAT2:DSPAB Bidirectional Data Bus input
25
DBDA:Debug data
26
DBCK:Debug clock
27
FDAT1:DSPAB Bidirectional Data Bus input
28
TEST:This pin is connected low for normal operation.
29
FDAT0:DSPAB Bidirectional Data Bus input
30
NV_WE, GPIO16:SRAM write enable output, General Purpose I/O
31
NV_OE, GPIO15:SRAM output Enable output, General Purpose I/O
32
NV_CS, GPIO14:SRAM Chip Select output, General Purpose I/O
33
SD_WE :SDRAM write enable output.
34
SD_DATA0, EXTD0:SDRAM data bus. SRAM external data bus input.
35
SD_DATA1, EXTD1:SDRAM data bus. SRAM external data bus input.
36
SD_DATA2, EXTD2:SDRAM data bus. SRAM external data bus input.
37
SD_DATA3, EXTD3:SDRAM data bus. SRAM external data bus input.
38
SD_DATA4, EXTD4:SDRAM data bus. SRAM external data bus input.
39
SD_DQM0:SDRAM data mask 0 output.
40
SD_DATA5, EXTD5:SDRAM data bus. SRAM external data bus input.
41
VSSSD4:3.3V SDRAM / SRAM / EPROM Interface ground.
42 VDDSD4:3.3V SDRAM / SRAM / EPROM Interface supply
43 SD_DATA6, EXTD6:SDRAM data bus. SRAM external data bus input.
44
SD_DATA7, EXTD7:SDRAM data bus. SRAM external data bus input.
45
SD_DQM1:SDRAM data mask 1 output.
46
SD_DATA15, EXTA18:SDRAM data bus output, SRAM external address bus output
47
SD_DATA14, EXTA17:SDRAM data bus output, SRAM external address bus output
48
NC5:No connect. Connect to ground.
DTR-7.6