Integra DTR-7.6 Service Manual page 104

IC BLOCK DIAGRAMS AND DESCRIPTIONS
MX26LV040-70/EN29LV040A(4M-bit CMOS High Speed Flash Memory)
BLOCK DIAGRAM
WE
OE
CE
A0~A18
BLOCK DIAGRAM
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE
8
Vcc
9
A18
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
CONTROL
PROGRAM/ERASE
INPUT
HIGH VOLTAGE
LOGIC
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
SENSE
AMPLIFIER
I/O BUFFER
Q0-Q7
PIN DESCRIPTION
32 OE
31 A10
30 CE
29
Q7
28
Q6
27
Q5
26
Q4
25
Q3
24 GND
23 Q2
22 Q1
21
Q0
20
A0
19
A1
18
A2
17
A3
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
SYMBOL PIN NAME
A0~A18 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
VCC Power Supply Pin (+5V)
GND Ground Pin
DTR-7.6