Integra DTR-7.6 Service Manual page 110

IC BLOCK DIAGRAMS AND DESCRIPTIONS
SiI9030(HDMI PanelLink Transmitter)
Pin # Pin Name
1 HSYNC
2 VSYNC
3 CGND
4 CVCC18
5 SPDIF
6 MCLK
7 SD3
8 SD2
9 SD1
10 SD0
11 WS
12 SCK
13 IOVCC
14 IOGND
15 CGND
16 CVCC18
17 INT
18 HPD
19 DSDA
20 DSCL
21 RSVDL
22 PGND1
23 PVCC1
24 EXT_SWING
25 AGND
26 TXC-
27 TXC+
28 AVCC
29 TX0-
30 TX0+
31 AGND
32 TX1-
33 TX1+
34 AVCC
35 TX2-
36 TX2+
37 AGND
38 PVCC2
39 PGND2
40 NC
41 CI2CA
42 RESET
43 CSCL
44 CSDA
45 CVCC18
46 CGND
47 IOGND
48 IOVCC
49 D23
50 D22
51 D21
52 D20
53 D19
54 D18
55 D17
56 D16
57 D15
58 D14
59 CVCC18
60 CGND
61 D13
62 D12
63 D11
64 D10
65 D9
66 IDCK
67 D8
68 D7
69 D6
70 D5
71 IOVCC
72 IOGND
73 CGND
74 CVCC18
75 D4
76 D3
77 D2
78 D1
79 D0
80 DE
I/O Description
I Horizontal Sync input control signal
I Vertical Sync input control signal
Digital core GND.
Digital core VCC. Connect to 1.8V supply.
I S/PDIF Audio input
I Audio Input Master Clock
I I2S Serial Data
I I2S Serial Data
I I2S Serial Data
I I2S Serial Data
I I2S Word Select
I I2S Serial Clock
IO Pin VCC. Connect to 3.3V supply.
IO Pin GND.
Digital core GND.
Digital core VCC. Connect to 1.8V supply.
O Interrupt Output.
I Hot Plug Detect Input.
I/O DDC data
I/O DDC Clock
I Reserved for use by Silicon image, and must be tied LOW.
TMDS Core PLL Ground.
TMDS Core PLL Power. Connect to 3.3V supply.
Voltage Swing Adjustment. The resistor between AVCC and this pin
I
determines the amplitude of the voltage swing.
Analog GND.
O
TMDS output clock.
O
Analog VCC. Connect to 3.3Vsupply.
O
TMDS output data.
O
Analog GND.
O
TMDS output data.
O
Analog VCC. Connect to 3.3Vsupply.
O
TMDS output data.
O
Analog GND.
Filter PLL Power. Connect to 3.3V supply.
Filter PLL Ground.
Not connected.
I I2C device address select
I Reset Pin. Active LOW
I I2C Clock
I/O I2C Data
Digital core VCC. Connect to 1.8V supply.
Digital core GND.
IO Pin GND.
IO Pin VCC. Connect to 3.3V supply.
I
I
I
I
12-bit Input Pixel Data Bus. These pins are used in 24-bit mode, single-
I
I edge mode.
I
I
I
I
Digital core VCC. Connect to 1.8V supply.
Digital core GND.
I
I
12-bit Input Pixel Data Bus. These pins are used in 24-bit mode, single-
I
edge mode.
I
I
I Input Data Clock
I
12-bit Input Pixel Data Bus. These pins are used in 24-bit mode, single-
I
I edge mode.
I
IO Pin VCC. Connect to 3.3V supply.
IO Pin GND.
Digital core GND.
Digital core VCC. Connect to 1.8V supply.
I
I
12-bit Input Pixel Data Bus. These pins are used in 24-bit mode, single-
I
edge mode.
I
I
I Data enable
Use
Video and Audio
Video and Audio
Ground
Power
Video and Audio
Video and Audio
Video and Audio
Video and Audio
Video and Audio
Video and Audio
Video and Audio
Video and Audio
Power
Ground
Ground
Power
Confirration/Programming
Confirration/Programming
Control
Control
Confirration/Programming
Ground
Power
Differential signal data
Ground
Differential signal data
Power
Differential signal data
Ground
Differential signal data
Power
Differential signal data
Ground
POwer
Ground
Control
Control
Control
Control
Power
Ground
Ground
Power
Video and Audio
Power
Ground
Video and Audio
Video and Audio
Video and Audio
Power
Ground
Ground
Power
Video and Audio
Video and Audio
DTR-7.6