Bit Timer Mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7) - Epson S1C63616 Technical Manual

4.9.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7)

Timers 0 and 1, Timers 2 and 3, Timers 4 and 5, and Timers 6 and 7 combinations can be used as 16-bit
timers.
To use Timers 0 and 1 as a 16-bit timer, write "1" to the Timer 0 16-bit mode select register MOD16_A.
The 16-bit timer is configured with Timer 0 for low-order byte and Timer 1 for high-order byte as shown in
Figure 4.9.6.1.
P12 P12 port
Timer 0
PTRUN0
Run/Stop
Timer 0
clock
f
OSC1
PTPS00–PTPS03
Clock
Timer 0 clock selection
manager
f
OSC3
f /16 (2,048Hz)
OSC1
Interrupt
Interrupt
control circuit
TOUT_A P13 port
Selector
Output control PTOUT_A
In 16-bit timer mode, the Timer 0 register settings are effective for timer RUN/STOP control and count clock
frequency selection. The event counter function can also be used. Timer 1 uses the Timer 0 underflow signal
as the count clock, therefore, the Timer 1 RUN/STOP control and count clock frequency select registers
become invalid. However, the PWM output function must be controlled using the Timer 1 control register.
Timer 1 output signal is automatically selected for the TOUT_A output (the TOUT_A output select register
is ineffective). The reload data must be preset to Timer 0 and Timer 1 separately using each PTRSTx register.
The counter data of a 16-bit timer must be read from the low-order 4 bits. In 16-bit timer mode, the high-
order data (PTD04–PTD17) is latched by reading the low-order 4 bits (PTD00–PTD03). The counter keeps
counting. However, the latched high-order data is maintained until the next reading of low-order data.
Therefore, after the low-order 4-bit data (PTD00–PTD03) is read, the high-order data (PTD04–PTD17) can
be read regardless of the order for reading. If data other than the low-order 4 bits (PTD00–PTD03) is read
first, the hold function is not activated. In this case, the correct counter data cannot be read.
The description above is applied when Timers 2 and 3, Timers 4 and 5 or Timers 6 and 7 are used as a 16-bit
timer.
Timer 0 + 1
Timer 0 reset
Timer 1 reset
Timer function setting FCSEL_A
Pulse polarity setting PLPUL_A
EVCNT_A
Event counter
mode setting
1/2
Fig. 4.9.6.1 Configuration of 16-bit timer (Timer 0 + 1)
Timer 0
Low-order 8 bits
Reload data register
PTRST0
RLD00–RLD07
PTRST1
8-bit down counter
Timer
control
circuit
Data buffer
PTD00–PTD07
Compare match signal
Compare data register
CD00–CD07
PWM waveform
generator
SIC63616-(Rev. 1.0) NO. P104
Timer 1
High-order 8 bits
Reload data register
RLD10–RLD17
8-bit down counter
Data buffer
PTD10–PTD17
Comparator
Compare data register
CD10–CD17
PTSEL1
PWM output selection
Underflow signal
3240-0412