Circuit Diagram - LG GX500 Service Manual

7. CIRCUIT DIAGRAM

12 11
L
BASE BAND PROCESSOR
K
J
2V62_VIO VBAT
W18
BAT_ID M_0
V17
S1_RF_TEMP M_1
Y19
M_2
Y18
M_3
W17
M_4
AA18
M_5
Y17
M_6
W16
M_7
AA17
M_8
Y16
M_9
U15
I M_10
K16
PA_LEVEL
PAOUT11
M12
PAOUT12
N15
I
BB_I
M15
IX BB_IX
M16
Q
BB_Q
K15
QX BB_QX
E13
TXON_PA T_OUT0
B14
WLAN_WAKEUP
T_OUT1
F11
S1_PA_BAND T_OUT2
A15
WLAN_ENABLE T_OUT3
E11
REG_ON T_OUT4
F12
SGR_INT T_OUT5
PA_MODE B13
R117 T_OUT6
C11
SGR_RESETN T_OUT7
H 100K
UART_SEL E12
T_OUT8
C12
TS_IRQ T_OUT9
WLAN_HOST_WAKEUP B12
T_OUT10
B15
LIN_MOTOR_EN T_IN0
C13
_CHG_EN
T_IN1
D17
RF_EN
RF_STR0
D18
_DPRAM_BUSY_S1 RF_STR1
E15
RF_DA RF_DATA
B17
RF_CLK RF_CLK
G C18
AFC
W12
_DPRAM_INT_S1 CLKOUT0
26MHZ_MCLK U12
F26M
H15
SWIF_TXRX
H16
SG3_SIM1_IO CC_IO
SG3_SIM1_CLK K18
CC_CLK
K17
SG3_SIM1_RST CC_RST
E10
WLAN_CMD MMCI1_CMD
A12
WLAN_CLK
MMCI1_CLK
B11
WLAN_SDIO[0] MMCI1_DAT0
C9
WLAN_SDIO[1]
MMCI1_DAT1
F10
WLAN_SDIO[2] MMCI1_DAT2
A14
WLAN_SDIO[3]
MMCI1_DAT3
D3
MMC_CMD MMCI2_CMD
D2
MMC_D0
MMCI2_DAT0
F F6
MMC_CLK MMCI2_CLK
W11
_DPRAM_SEM_S1 FWP
2V62_VIO
F2
USB_OEN IRDA_TX
G2
BT_HOST_WAKEUP IRDA_RX
2V62_VIO
A18
TDO
B18
TDI
C15
TMS
C16
TCK
F13
TRST_N
F16
RTCK
E14
TRIG_IN
B16
MON1
C10
MON2
AA7
E TRACESYNC
U11
TRACECLK
Y9
PIPESTAT2
T10
PIPESTAT1
Y8
PIPESTAT0
D
KEY_ROW0
KEY_ROW1
KEY_ROW4
C
B
UART
V_BUS VBAT
UT101
3G 2.5G
1
GND GND
2 UART_RX
RX RX
3
TX TX UART_TX
4
VCHAR NC1
5
ON_SW ON_SW RPWRON_EN
6
VBAT VBAT
A 7
PWR NC2
8
USB_DM
URXD NC3
9
UTXD NC4 USB_DP
10
SIM1_DSR
DSR
11
RTS
12
CTS
12 11
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
10 9 8
1V35_CORE 1V8_SD 2V62_VIO 2V62_VIO 2V11_RTC 2V5_VAUDB
1V8_SD 2V9_SIM 1V35_VPLL 2V5_VAUDA
U101
2V62_VIO
FL101
1 9
INOUT_A1 INOUT_B1
2 8
INOUT_A2 INOUT_B2
3 7
INOUT_A3 INOUT_B3
4 6
INOUT_A4 INOUT_B4
C139 C145
22N 22N
7.5pF
2V62_VIO
FL102
1 9
KEY_COL0 INOUT_A1 INOUT_B1
2 8
KEY_COL1
INOUT_A2 INOUT_B2
3 7
KEY_COL2 INOUT_A3 INOUT_B3
4 6
KEY_COL3
INOUT_A4 INOUT_B4
7.5pF
10 9 8
7 6 5 4
U8 S1_ADD[0]
MEM_A0
W4
S1_ADD[1]
MEM_A1
T8 S1_ADD[2]
MEM_A2
U6
S1_ADD[3]
MEM_A3
W5 S1_ADD[4]
MEM_A4
AA4
MEM_A5 S1_ADD[5]
T7 S1_ADD[6]
MEM_A6
U7
MEM_A7 S1_ADD[7]
Y5 S1_ADD[8]
MEM_A8
AA5
MEM_A9 S1_ADD[9]
W6 S1_ADD[10]
MEM_A10
T9
MEM_A11 S1_ADD[11]
W7 S1_ADD[12]
MEM_A12
Y6 S1_ADD[13]
MEM_A13 1V8_SD
U9 S1_ADD[14]
MEM_A14
W9 S1_ADD[15]
MEM_A15
V1
S1_ADD[16]
MEM_A16
N5 S1_ADD[17]
MEM_A17
U2
S1_ADD[18]
MEM_A18
W2 S1_ADD[19]
MEM_A19
R5
S1_ADD[20]
MEM_A20
T1 S1_ADD[21]
MEM_A21
R4
S1_ADD[22]
MEM_A22
T2 S1_ADD[23]
MEM_A23
P5
S1_ADD[24]
MEM_A24
T3 S1_ADD[25]
MEM_A25
T4
MEM_A26 S1_ADD[26]
M2
MEM_AD0 S1_DATA[0]
L3 S1_DATA[1]
MEM_AD1
J3
MEM_AD2 S1_DATA[2]
L5 S1_DATA[3]
MEM_AD3
M3
MEM_AD4 S1_DATA[4]
N1 S1_DATA[5]
MEM_AD5
P2 S1_DATA[6]
MEM_AD6
N2
S1_DATA[7]
MEM_AD7
J4 S1_DATA[8]
MEM_AD8
K4
S1_DATA[9]
MEM_AD9
K5 S1_DATA[10]
MEM_AD10
L4
S1_DATA[11]
MEM_AD11
R1 S1_DATA[12]
MEM_AD12
M5
S1_DATA[13]
MEM_AD13
M4 S1_DATA[14]
MEM_AD14
P4
S1_DATA[15]
MEM_AD15
R2
MEM_CS0_N _NAND_CS_S1
P3
MEM_CS1_N _RAM_CS_S1
N3
MEM_CS2_N _DPRAM_CS_S1
N4
MEM_CS3_N
U3
MEM_CSA0_N S1_ADD[27]
U4 S1_ADD[28]
MEM_CSA1_N
T6
MEM_CSA2_N S1_ADD[29]
T5 S1_ADD[30]
MEM_CSA3_N
T11 S1_FCDP
FCDP_RBN
K2
MEM_WAITN
M1
MEM_ADVN
L1
_RD_S1
MEM_RDN
R3
MEM_WRN _WR_S1
W3
MEM_BFCLKO1
Y3
S1_SDCLKI
MEM_BFCLKO2 R104 22
Y2
MEM_SDCLKO S1_SDCLKO
AA2
_BC0_S1
MEM_BC0_N
V3
MEM_BC1_N _BC1_S1
U5
MEM_BC2_N _BC2_S1
Y4 _BC3_S1
MEM_BC3_N
Y7 _RAS_S1
MEM_RAS_N
W8
MEM_CAS_N _CAS_S1
U10 S1_CKE
MEM_CKE
32.768KHz
AA16
F32K
AA15 2 1
OSC32K
W14
_RESET
RESET_N X101
H18 C144 C140
RSTOUT_N SIM1_DSR
Y14 22P 22P
RTC_OUT
RTC_OUT
R16
VREFP
R15
IREF
J18
SPCU_RQ_IN0
J19
SPCU_RQ_IN1
H17 VREFN
SPCU_RC_OUT0
G18
SPCU_RQ_IN2
TP112 TP110
7 6 5 4
- 121 -
3 2 1
2G NAND(LB/128Mx16bit) +1G SDR SDRAM(8Mx4x32bit)
EUSY0347505, Hynix
K4
A0 S1_ADD[16]
TP105
S1_DATA[0] N1 L1
IO0 A1 S1_ADD[17]
N2 L2
S1_DATA[1] IO1 A2 S1_ADD[18]
S1_DATA[2] N3 L3 S1_ADD[19]
IO2 A3
M5 C2
1V8_SD S1_DATA[3] IO3 A4 S1_ADD[20]
S1_DATA[4] P7 D2 S1_ADD[21]
IO4 A5
M6 E1
S1_DATA[5] IO5 A6 S1_ADD[22]
S1_DATA[6] N6 D3 S1_ADD[23]
IO6 A7
M8 E2
S1_DATA[7] IO7 A8 S1_ADD[24]
S1_DATA[8] P2 D4 S1_ADD[25]
IO8 A9
P3 K3
S1_DATA[9] IO9 A10 S1_ADD[26]
S1_DATA[10] N4 F2
IO10 A11 S1_ADD[27]
P4 F1
S1_DATA[11] IO11 A12 S1_ADD[28]
P5 J3
S1_DATA[12] S1_ADD[29]
IO12 BA0
N7 K2
S1_DATA[13] IO13 BA1 S1_ADD[30]
M7
S1_DATA[14]
IO14
N8 L4
R113 100K S1_DATA[15] IO15 DQ0 S1_DATA[0]
L5
S1_DATA[1]
DQ1
B6 L6
_NAND_CS_S1 _CE DQ2 S1_DATA[2]
TP106 B3 L7
_RD_S1 _RE DQ3 S1_DATA[3]
TP109
B7 K8 S1_DATA[4]
_WR_S1 _WEN DQ4
TP111 B4 L8
S1_ADD[17] CLE DQ5 S1_DATA[5]
S1_ADD[16] C4 K7 S1_DATA[6]
ALE DQ6
C3 K5
_WP DQ7 S1_DATA[7]
C6 K6 S1_DATA[8]
S1_FCDP R_B DQ8
G7
DQ9 S1_DATA[9]
B5 J6 S1_DATA[10]
VCCN0 DQ10
N5 J5
VCCN1 DQ11 S1_DATA[11]
H6 S1_DATA[12]
U102 DQ12
C5 H5
VSSN0 DQ13 S1_DATA[13]
H8ACS0SJ0BCR-46M
P6 J4 S1_DATA[14]
VSSN1 DQ14
G3
DQ15 S1_DATA[15]
TP104
B8 G4 S1_ADD[0]
VDD0 DQ16
D1 F4
VDD1 DQ17 S1_ADD[1]
H1 E4
S1_ADD[2]
VDD2 DQ18
H10 F5
VDD3 DQ19 S1_ADD[3]
P8 H3
S1_ADD[4]
VDD4 DQ20
M1 H4
VDD5 DQ21 S1_ADD[5]
E6
DQ22 S1_ADD[6]
C107 C104 C116 C117 C113 C110 C120 C135 B9 F7 S1_ADD[7]
VSS0 DQ23
C1 F6
VSS1 DQ24 S1_ADD[8]
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
H9 D5 S1_ADD[9]
VSS2 DQ25
J1 E8
VSS3 DQ26 S1_ADD[10]
P9 D6 S1_ADD[11]
VSS4 DQ27
M2 D8
VSS5 DQ28 S1_ADD[12]
D7 S1_ADD[13]
DQ29
J10 C8
VDDQ0 DQ30 S1_ADD[14]
K9 C7 S1_ADD[15]
VDDQ1 DQ31
L9
VDDQ2
R107 22
M10 J2
VDDQ3 _CS S1_SDCLKI
N9 G8
VDDQ4 CK S1_SDCLKO
TP108
C9 E3
VDDQ5 CKE S1_CKE
D10 K1
VDDQ6 _WED _WR_S1
E9 G2 TP107
_RAS_S1 1V8_SD
VDDQ7 _RAS TP102
F10 H2
VDDQ8 _CAS _CAS_S1
G9 J8 TP103
_BC0_S1
VDDQ9 DQM0
G6
DQM1 _BC1_S1
J9 F8
VSSQ0 DQM2 _BC2_S1
K10 E7
VSSQ1 DQM3 _BC3_S1
L10
VSSQ2
C143 C138 C126 C125 C118 C133 C127 C102 C136 C103 M9 A2
VSSQ3 DNU0
N10 A9
VSSQ4 DNU1
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
C10 A10
VSSQ5 DNU2 _RAM_CS_S1
D9 R1
VSSQ6 DNU3
E10 R2
VSSQ7 DNU4
F9 R9
VSSQ8 DNU5
G10 R10
VSSQ9 DNU6
ON BOARD ARM9 JTAG & ETM INTERFACE
3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
LGE Internal Use Only