LG GX500 Service Manual page 124

7. CIRCUIT DIAGRAM
12 11
L
VRF3_2V85 VRF3_2V85
K
VRF3_2V85
C514 C535 C538
10n
10n 0.1u
J
100p 0.1u
C542 C512
VRF2_1V5
VSD2_1V8
VSD1_1V5
C505 C533
C511
100n 100n
S2_VBAT
100n
H3
BAT_ID M0
J3
S2_RF_TEMP
M1
I G4
M2
H4
M7
G3
M8
J4
M9
F4
M10
TXHB W3
TX2
V3
TXLB TX1
GSM850_RXP W2
RX1
V1
GSM850_RXN RX1X
GSM900_RXP U1
RX2
T1
GSM900_RXN RX2X
R3
PABIAS
R4
S2_PA_BAND PABS
R1
DCS1800_RXP
RX3
T5
VDET
U5
H
PAMODE
P1
DCS1800_RXN RX3X
N4
VC1
FE1
P5
VC2 FE2
M3
PA_EN
PAEN
N1
PCS1900_RXP RX4
P3
TX_RAMP VRAMP
PCS1900_RXN M1
RX4X
A18
T_OUT3
J10
T_OUT4
H11
T_OUT5
PA_MODE_2 E13
T_OUT6
B19
T_OUT7
K9
T_OUT8
TP501 G19
G CLKOUT0
X502 DSX321SG-26M U4
REFR
W7
4 3 XOX
W8
1 2
XO
V10
SGR_SIM2_IO
CC_IO
U9
26MHz SGR_SIM2_CLK CC_CLK
V9
SGR_SIM2_RST CC_RST
U10
MMCI_CMD
R8
MMCI_DAT0
R10
MMCI_CLK
_DPRAM_INT_S2 T9
MMCI_DAT1
R9
_DPRAM_BUSY_S2 MMCI_DAT2
T10
MMCI_DAT3
VIO_2V62 VIO_2V62
T8
F TDO
T7
TDI
U8
TMS
V8
TCK
W9
TRST_N
R6
RTCK
N5
TRIG_IN
L5
R509 10K MON1
M5
MON2
S2_VBAT
VSD1_1V5
R7
FSYS3
U7
FSYS2
A14
VBAT_SD1
A15
VSD1
A13
SD1_FB
E VSD2_1V8 C11
SD2_SD1_SUBST
C523 A12
VSS_SD1
A16
22u SD1_FBL
A11
VBAT_SD2
A10
VSD2
C520 C506 10u L 509 B9
SD2_FB
B10
SD2_FBL
10u 10u C540 A9
VSS_SD2
22u
C12
SU_GATE
B14
SU_GND
B11
SU_FB
B13
SU_ISENSE
B12
VBAT_SU
C13
VSS_SU
D
C
B
A
12 11
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
10 9 8
VRF3_2V85 VUSB_3V1
VAUDIO_2V5
S2_VBAT VRF2_1V5
VRF3_2V85
VBT_2V9
VRF1_2V85 C530 VPLL_1V5
1u
C527 C521
C528 C539
1u 0.47u 2.2u
2.2u C532
C508 C534 C529 C503 C518
1u
C509
10n 0.1u 10n 0.1u 1u
VMMC_1V8
2.2u
VRTC_2V0
C531 VIO_2V62 VRF1_2V85
VRF3_2V85 S2_VBAT VSIM_2V9
2.2u
S2_VBAT
C510
C504
1u C517 C515 C513
1u 220n 1u
2.2u
U503
TP504 TP505
C536 C507
15p 15p
L501 L506 L502 L507
100n 100n 100n 100n
VIO_2V62
VIO_2V62
10 9 8
7 6 5 4
SGR_RPWRON_EN
_RAM_CS_S2
R14
S2_DATA[0]
EBU_AD0
W18 S2_DATA[1]
EBU_AD1
V18
EBU_AD2 S2_DATA[2]
W17 S2_DATA[3]
EBU_AD3
T15
EBU_AD4 S2_DATA[4]
U14 S2_DATA[5]
EBU_AD5
V17
EBU_AD6 S2_DATA[6]
T14 S2_DATA[7]
EBU_AD7
R13
EBU_AD8 S2_DATA[8]
W16 S2_DATA[9]
EBU_AD9
V16 S2_DATA[10]
EBU_AD10
U12 S2_DATA[11]
EBU_AD11
W15 S2_DATA[12]
EBU_AD12 VSD2_1V8
W14
S2_DATA[13]
EBU_AD13
V15 S2_DATA[14]
EBU_AD14
W13
S2_DATA[15]
EBU_AD15
N18
EBU_WR_N _WR_S2
P19
_RD_S2
EBU_RD_N
N19
EBU_BC0_N _BC0_S2
P15
_BC1_S2
EBU_BC1_N
R526
M_RESET
H19
EBU_A0 S2_ADD[0] C544
J17 S2_ADD[1] S2_FCDP 15p
EBU_A1
K16
EBU_A2 S2_ADD[2]
G18 S2_ADD[3]
EBU_A3
L16 S2_ADD[4]
EBU_A4
J19 S2_ADD[5]
EBU_A5
J16 S2_ADD[6]
EBU_A6
K17
S2_ADD[7]
EBU_A7
K18 S2_ADD[8]
EBU_A8
L17
S2_ADD[9]
EBU_A9
K15 S2_ADD[10]
EBU_A10
L18
S2_ADD[11]
EBU_A11
M16 S2_ADD[12]
EBU_A12
J18
S2_ADD[13]
EBU_A13
M18 S2_ADD[14]
EBU_A14
N15
EBU_A15
L15 S2_ADD[16]
EBU_A16
L19
EBU_A17 S2_ADD[17]
M15
EBU_A18
M19
EBU_A19
H18
EBU_A20
R16
EBU_A21
N17
EBU_A22
T19
EBU_A23
U17
EBU_A24
R17
EBU_CS0_N _NAND_CS_S2
R19
_RAM_CS_S2
EBU_CS1_N
T17
EBU_CS2_N _DPRAM_CS_S2
P18 TP502
EBU_CS3_N
R18
EBU_ADV_N
K19
_RAS_S2
EBU_RAS_N
N16
EBU_CAS_N _CAS_S2
U18
EBU_WAIT_N
R519 22
U19
EBU_SDCLKO S2_SDCLKO
U15
EBU_SDCLKI S2_SDCLKI
P17
EBU_BFCLKO
U16
EBU_BFCLKI
T18 S2_CKE
EBU_CKE
F18
FCDP_RBN S2_FCDP
E19
F32K
D19
OSC32K 32.768KHz
F19
FC-135
RESET_N
2 1
X501
B5 C541 C524
IREF1
B6
22p 22p
A_GND
A6
VREF1
L3
VREF2
L4
IREF2
C519 C526
220n 1u
NRESET
TP506
PO_RESET
M_RESET
R504
PWRON
DNI
VRTC_2V0
R508
VRTC_2V0
2K
3
Q501 R511
2
SGR_PWR_ON
10K
1
7 6 5 4
- 125 -
3 2 1
1G NAND(LB/64Mx16bit) +512M SDR SDRAM(8Mx4x16bit)
EUSY0389001, SS
S2_DATA[0] B3 J5 S2_DATA[0]
DQ0 IO0
S2_DATA[1] C4 L5 S2_DATA[1]
DQ1 IO1
S2_DATA[2] C3 J6 S2_DATA[2]
DQ2 IO2
D4 L6
S2_DATA[3] S2_DATA[3]
DQ3 IO3
S2_DATA[4] D3 J7 S2_DATA[4]
DQ4 IO4
E4 L7
S2_DATA[5] S2_DATA[5]
DQ5 IO5
S2_DATA[6] E3 J8 S2_DATA[6]
DQ6 IO6
F4 L8
VSD2_1V8 S2_DATA[7] S2_DATA[7]
DQ7 IO7
S2_DATA[8] J4 K5 S2_DATA[8] VSD2_1V8
DQ8 IO8
K3 M5
S2_DATA[9] S2_DATA[9]
DQ9 IO9
S2_DATA[10] K4 K6 S2_DATA[10]
DQ10 IO10
L3 M6
S2_DATA[11] S2_DATA[11]
DQ11 IO11
S2_DATA[12] L4 K7 S2_DATA[12]
DQ12 IO12
M3 M7
S2_DATA[13] DQ13 IO13 S2_DATA[13]
S2_DATA[14] M4 K8 S2_DATA[14]
DQ14 IO14
N3 M8 VSD2_1V8
S2_DATA[15] DQ15 IO15 S2_DATA[15]
R524 22
E9
S2_SDCLKI _CS
S2_SDCLKO H4 B4
CLK VDD1
G8 G9
S2_CKE CKE VDD2
_WR_S2 F8 H2
_WED VDD3
D7 M2
S2_ADD[13] BA0 VDD4
D8 U502
S2_ADD[14]
BA1
E7
_RAS_S2 _RAS
F7 D2
_CAS_S2
_CAS VDDQ1
G3 F2
_BC0_S2 LDQM VDDQ2
H3 K2
_BC1_S2
UDQM VDDQ3
C7
S2_ADD[0] C545 C546
A0
S2_ADD[1] C8 C2
A1 VSS1 470n 220n
C9 F9
S2_ADD[2]
A2 VSS2
S2_ADD[3] B8 G2
A3 VSS3
M9 N4
S2_ADD[4] A4 VSS4 VSD2_1V8
VSD2_1V8 S2_ADD[5] L9
A5
K9
S2_ADD[6] A6
S2_ADD[7] J9 E2
A7 VSSQ1
H7 J2
S2_ADD[8] A8 VSSQ2
S2_ADD[9] H8 L2
A9 VSSQ3
D9
S2_ADD[10] A10
S2_ADD[11] H9
A11
S2_ADD[12] G7 B6
A12 VCC1
N7
VCC2
C6
_NAND_CS_S2 _CE
D5 N6
S2_ADD[16]
ALE VCCQ
C5
S2_ADD[17] CLE
E5
_RD_S2
_RE
E6 B5 C547
R__B VSS5
D6 N5 470n
100 _WR_S2
_WE VSS6
F5 N8
_WP VSS7
C543
15p
EXT_RESET
VIO_2V62 VRTC_2V0
U501
7 8
A1 VCC R513 DNI
6 1
PO_RESET B1 Y1
R516 DNI
NRESET 5 2
Y2 B2
4 3
GND A2 SGR_RESETN
C502
100n
ON BOARD ARM9 JTAG & ETM INTERFACE
3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
LGE Internal Use Only