LG GX500 Service Manual page 50

GX500 Operational Description
_RAM_CS_S2
VSD2_1V8
R526
M_RESET
S2_FCDP
Figure 3-14 SGold Radio Part Flash memory & SDR RAM MCP circuit diagram
LG Electronics
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
1G NAND(LB/64Mx16bit) +512M SDR SDRAM(8Mx4x16bit)
B3
S2_DATA[0]
C4
S2_DATA[1]
C3
S2_DATA[2]
D4
S2_DATA[3]
D3
S2_DATA[4]
E4
S2_DATA[5]
E3
S2_DATA[6]
VSD2_1V8 F4
S2_DATA[7]
J4
S2_DATA[8]
K3
S2_DATA[9]
K4
S2_DATA[10]
L3
S2_DATA[11]
L4
S2_DATA[12]
M3
S2_DATA[13]
M4
S2_DATA[14]
N3
S2_DATA[15]
R524 22
E9
S2_SDCLKI
H4
S2_SDCLKO
G8
S2_CKE
F8
_WR_S2
D7
S2_ADD[13]
D8
S2_ADD[14]
E7
_RAS_S2
F7
_CAS_S2
G3
_BC0_S2
H3
_BC1_S2
C7
S2_ADD[0]
C8
S2_ADD[1]
C9
S2_ADD[2]
B8
S2_ADD[3]
M9
S2_ADD[4]
L9
VSD2_1V8
S2_ADD[5]
K9
S2_ADD[6]
J9
S2_ADD[7]
H7
S2_ADD[8]
H8
S2_ADD[9]
D9
S2_ADD[10]
H9
S2_ADD[11]
G7
S2_ADD[12]
C6
_NAND_CS_S2
D5
S2_ADD[16]
C5
S2_ADD[17]
E5
_RD_S2
E6
D6
_WR_S2
100
F5
C544 C543
15p 15p
EUSY0389001, SS
DQ0 IO0
DQ1 IO1
DQ2 IO2
DQ3 IO3
DQ4 IO4
DQ5 IO5
DQ6 IO6
DQ7 IO7
DQ8 IO8
DQ9 IO9
DQ10 IO10
DQ11 IO11
DQ12 IO12
DQ13 IO13
DQ14 IO14
DQ15 IO15
_CS
CLK VDD1
CKE VDD2
_WED VDD3
BA0 VDD4
U502
BA1
_RAS
_CAS VDDQ1
LDQM VDDQ2
UDQM VDDQ3
A0
A1 VSS1
A2 VSS2
A3 VSS3
A4 VSS4
A5
A6
A7 VSSQ1
A8 VSSQ2
A9 VSSQ3
A10
A11
A12 VCC1
VCC2
_CE
ALE VCCQ
CLE
_RE
R__B VSS5
_WE VSS6
_WP VSS7
51/143
- 51 -
3. TECHNICAL BRIEF
Revision A
J5
S2_DATA[0]
L5
S2_DATA[1]
J6
S2_DATA[2]
L6
S2_DATA[3]
J7
S2_DATA[4]
L7
S2_DATA[5]
J8
S2_DATA[6]
L8
S2_DATA[7]
K5 VSD2_1V8
S2_DATA[8]
M5
S2_DATA[9]
K6
S2_DATA[10]
M6
S2_DATA[11]
K7
S2_DATA[12]
M7
S2_DATA[13]
K8
S2_DATA[14]
M8 VSD2_1V8
S2_DATA[15]
B4
G9
H2
M2
D2
F2
K2
C545 C546
C2
470n 220n
F9
G2
N4
VSD2_1V8
E2
J2
L2
B6
N7
N6
C547
B5
N5 470n
N8
LGE Property
LGE Internal Use Only