Eeprom Control - Oki OKIPAGE 8p Maintenance Manual

3.4

EEPROM Control

The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64-
bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred
in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock
signal from the CPU.
The EEPROM operates in the following instruction modes.
Instruction
Read (READ)
Write Enabled (WEN)
Write (WRITE)
Write All Address (WRAL)
Write Disabled (WDS)
Erase
Chip Erasable (ERAL)
Write cycle timing (WRITE)
CS
SK
1 2
DI 1 0
DO
HIGH-Z
Read cycle timing (READ)
CS
1 2
SK
1 1
DI
DO
HIGH-Z
154
CPU
150
151
Start bit
1
1
1
1
1
1
1
4
A5 A4 A1
1
4
A5 A4 A1
0
3
SSTXD-P
1
EEPRMCSO-P
EEPRMCLK-P
Operation
code
10
00
01
00
00
11
00
9 10
A0 D15 D14
9 10
A0
0 D15 D14
- 7 -
IC4
DI DO
4
EEPROM
CS
SK
2
Address
A5 to A0
11XXXX
A5 to A0 D15 to D0
01XXXX D15 to D0
00XXXX
A5 to A0
10XXXX
Min. 450 ns
STATUS
25
D1 D0
Max. 500 ns
BUSY READY
Max. 10 ms
25 26
D1 D0 D15 D14
Data