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Timing Mode (Auto)
This item allows you to set up the DRAM timing manually or automatically.
•
Memclock index value (Mhz) (200MHz): When DDR Timing Setting by is
set to Manual, use this item to set the DRAM frequency.
•
CAS# latency (Tcl) (2.5): This item determines the operation of SDRAM
memory CAS (column address strobe). It is recommended that you leave this
item at the default value. The 2T setting requires faster memory that specifi-
cally supports this mode.
•
Min RAS# to active time (Tras) (8T): This item determines the time RAS
takes to read from and write to a memory cell.
•
RAS to CAS Delay (Trcd) (4T): This is the amount of time a CAS is per-
formed after a RAS. The lower the better, but some DRAM does not s u p -
port low figures.
•
Row precharge Time (Trrd) (2T): This item specifies the Row precharge
to Active or Auto-Refresh of the same bank.
•
Row to Row delay (Trrd) (2T): This item specifies the active-to-active
delay of different banks.
•
Row cycle time (Trc) (12T): This item determines the minimum number
of clock cycles a memory row takes to complete a full cycle, from row
activation up to the precharging of the active row.
•
Row refresh cyc time (Trfc) (24T): Auto-refreshactive to RAS#-active
or RAS# auto-refresh.
User Config mode (Auto)
This item has the capacity to automatically detect all of the following fields default
values. This item is set to [Auto] by default. When setting to [Manual], the following
items are adjustable.
•
1T/2T Memory Timing (2T): This item controls the SDRAM command rate.
•
Read Preamble value (6ns): This item allows you to set Read Preamble
value from 2ns, to 9.5ns, and it is specified in units of 0.5ns.
•
Async Latency value (6ns): This item allows you to set Async Latency
value from 2ns to 11ns, and it is specified in units of 1 ns.
Press <Esc> to return to the Advanced Chipset Features page.
LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
LDT Configuration
Upstream LDT Bus Width
Downstream LDT Bus Width
LDT Bus Frequency
PCIE Reset Delay
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values
Phoenix-AwardBIOS CMOS Setup Utility
LDT & PCI Bus Control
[Enabled]
[16 bit]
[16 bit]
[Auto]
[Disabled]
F6:Fail-Safe Defaults
Using BIOS
Item Help
Menu Level
F7:Optimized Defaults
35
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