Figure 4-23. Digital Pattern Generator Data Path; Figure 4-24. Digital Pattern Generation Timing - National Instruments DAQArb 5411 User Manual

Chapter 4 Arb Operation
Note:
DAQArb 5411 User Manual
Clock
Pattern Enable
*Output Enable

Figure 4-23. Digital Pattern Generator Data Path

You can enable or disable digital pattern generation through software.
All linking and looping capabilities are available for digital pattern
generation, as well. If you select DDS mode, the DDS data appears at
the digital I/O connector.
You can use digital pattern generation to test digital devices such as
serial and parallel DACs and to emulate protocols.
At computer power-up and reset, pattern generation is disabled.
Figure 4-24 shows the timing waveforms for digital pattern generation;
t is the clock time period and t
clk
on pattern lines, such as PA <0..15>. Refer to the Appendix A,
Specifications, for these timing parameters.
Clock
Data
16
OE*
is time delay from clock to output
co
t
clk
D
n
t
co

Figure 4-24. Digital Pattern Generation Timing

4-26
80
Line Out
16
Digital Pattern Out
50
Clock Out
D
n+1
© National Instruments Corporation
D
n+2