Advanced Chipset Features Option - ECS P4IBMS Instruction Manual

Advanced Chipset Features Option

These items define critical timing parameters of the main-
board. You should leave the items on this page at their default
values unless you are very familiar with the technical specifi-
cations of your system hardware. If you change the values
incorrectly, you may introduce fatal errors or recurring instabil-
ity into your system.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
DRAM Timing Selectable
CAS Latency Time
Active to Precharge Del ay
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
DRAM Data Integrity Mode
Memory Frequency For
System BIOS Cach eable
Video RAM Cacheable
Memory Hole At 15M -16M
Delayed Transaction
AGP Aperture Size (MB)
Delay Prior to Thermal
↑ ↓ → ← : Move Enter : Select
F5:Previous Values
DRAM Timing Selectable (Manual)
The value in this field depends on performance parameters of
the installed memory chips (DRAM). Do not change the value
from the factory setting unless you install new memory that
has a different performance rating than the original DRAMs.
CAS Latency Time: (3)
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not
reset this field from the default value specified by the system
designer.
Active to Precharge Delay (7)
The precharge time is the number of cycles it takes for DRAM
to accumulate its charge before refresh.
DRAM RAS# to CAS# Delay (3)
This field lets you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from,
Advanced Chipset Features
[Manual]
[3]
[7]
[3]
[3]
[Non-ECC]
[Auto]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[64]
[16 Min]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
45
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults