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3 7 63 1515 0
MB-134 BOARD IC1201 LAN8700C-AEZG-CTI (ETHERNET INTERFACE)
Pin No.
Pin Name
1
2
3
4
5
6
7
8
VDD_CORE
9 to 12
PA0 to PA3
13
14
15 to 18
RXD3 to RXD0
19
20
21
22
23, 24
TXD0, TXD1
25
26, 27
TXD2, TXD3
28
29
30
31
32
33
34
TE
L 13942296513
35
36
www
.
http://www.xiaoyu163.com
I/O
TX_ER
I
Transmit error signal input from the BD decoder
MDC
I
Serial data transfer clock signal input from the BD decoder
CRS
O
Carrier sense signal output to the BD decoder
MDIO
I/O
Two-way data bus with the BD decoder
nRST
I
Reset signal input from the system controller
TX_EN
I
Transmit enable signal input from the BD decoder
VDD33
-
Power supply terminal (+3.3V)
-
Power supply terminal (+1.8V)
-
Not used
XTAL2
O
System clock output terminal (25 MHz)
REFCLK
I
System clock input terminal (25 MHz)
O
Receive data output to the BD decoder
RX_DV
O
Receive data valid signal output to the BD decoder
RX_CLK
O
Receive clock signal output to the BD decoder
RX_ER
O
Receive error signal output to the BD decoder
TX_CLK
O
Transmit clock signal output to the BD decoder
I
Transmit data input from the BD decoder
VDDIO
-
Power supply terminal (+3.3V)
I
Transmit data input from the BD decoder
TXN
O
Serial data (negative) output to the ethernet connector
TXP
O
Serial data (positive) output to the ethernet connector
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
RXN
I
Serial data (negative) input from the ethernet connector
RXP
I
Serial data (positive) input from the ethernet connector
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
EXRES1
I
Reference resistor connection terminal
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
COL
O
Collision detect signal output to the BD decoder
x
ao
y
i
http://www.xiaoyu163.com
8
Not used
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
m
co
HBD-E770W
9 9
2 8
9 9
89
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