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HBD-E770W
QQ
3 7 63 1515 0
Pin No.
Pin Name
BA21
A_RCLK0B
BA23
A_RA8
BA25
A_RA12
BA27
A_RA7
BA29
A_RCKE
BA31
A_RDQ20
BA33
A_RDQS2
BA35
A_RDQS3B
BA37
A_RDQ26
BA39
A_RCLK1
BA41
DVSS
BA43
VCC2IO
BB2
SRXN_1
BB4
SRXN_2
BB6
SVCTST
BB8
XTAL25MI
BB10
TDO
BB12
TDI
BB14
VCC2IO
BB16
A_RDQS0B
BB18
VCC2IO
BB20
A_RDQ10
BB22
VCC2IO
BB24
A_RRASB
BB26
VCC2IO
BB28
A_RBA0
BB30
VCC2IO
TE
L 13942296513
BB32
A_RDQ17
BB34
VCC2IO
BB36
A_RDQ31
BB38
VCC2IO
BB40
A_TP_MEMPLL
BB42
VCC2IO
BC1
SRXP_1
BC3
STXP_1
BC5
STXP_2
BC7
AVDD33_XTAL25M
BC9
GPIO7
BC11
TMS
BC13
A_RDQ2
BC15
A_RDQ7
BC17
A_RDQS1
BC19
A_RDQ13
BC21
A_RCLK0
BC23
A_RA0
BC25
A_RA6
BC27
A_RA3
BC29
A_RWEB
BC31
A_RDQ19
BC33
A_RDQS2B
BC35
A_RDQS3
BC37
A_RDQ29
BC39
A_RCLK1B
www
BC41
A_TN_MEMPLL
BC43
A_REXTDN
.
88
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I/O
O
Clock signal (negative) output to the SD-RAM
O
Address signal output to the SD-RAM
O
Address signal output to the SD-RAM
O
Address signal output to the SD-RAM
O
Clock enable signal output to the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal (positive) output to the SD-RAM
O
Data strobe signal (negative) output to the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Clock signal (positive) output to the SD-RAM
-
Ground terminal
-
Power supply terminal (+1.8V)
I
SATA channel 1 RX differential pair signal (negative) input terminal
I
SATA channel 2 RX differential pair signal (negative) input terminal
-
Not used
I
System clock signal input terminal (25 MHz)
-
Not used
-
Not used
-
Power supply terminal (+1.8V)
O
Data strobe signal (negative) output to the SD-RAM
-
Power supply terminal (+1.8V)
I/O
Two-way data bus with the SD-RAM
-
Power supply terminal (+1.8V)
O
Row address strobe signal output to the SD-RAM
-
Power supply terminal (+1.8V)
O
Bank address signal output to the SD-RAM
-
Power supply terminal (+1.8V)
I/O
Two-way data bus with the SD-RAM
-
Power supply terminal (+1.8V)
I/O
Two-way data bus with the SD-RAM
-
Power supply terminal (+1.8V)
-
Not used
-
Power supply terminal (+1.8V)
I
SATA channel 1 RX differential pair signal (positive) input terminal
O
SATA channel 1 TX differential pair signal (positive) output terminal
O
SATA channel 2 TX differential pair signal (positive) output terminal
-
Power supply terminal (+3.3V)
-
Not used
-
Not used
I/O
Two-way data bus with the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal (positive) output to the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Clock signal (positive) output to the SD-RAM
O
Address signal output to the SD-RAM
O
Address signal output to the SD-RAM
O
Address signal output to the SD-RAM
O
Write enable signal output to the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal (negative) output to the SD-RAM
O
Data strobe signal (positive) output to the SD-RAM
I/O
Two-way data bus with the SD-RAM
O
Clock signal (negative) output to the SD-RAM
-
Not used
x
ao
u163
-
Not used
y
i
http://www.xiaoyu163.com
2 9
8
Description
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
Not used
0 5
8
2 9
9 4
2 8
Not used
m
9 9
9 9
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