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User Manuals: Phytec phyCARD-M Hardware Motherboard
Manuals and User Guides for Phytec phyCARD-M Hardware Motherboard. We have
1
Phytec phyCARD-M Hardware Motherboard manual available for free PDF download: Hardware Manual
Phytec phyCARD-M Hardware Manual (128 pages)
Brand:
Phytec
| Category:
Motherboard
| Size: 3 MB
Table of Contents
Table of Contents
3
Index of Figures
5
Index of Tables
7
Conventions, Abbreviations and Acronyms
9
Table 1: Abbreviations and Acronyms Used in this Manual
10
Preface
11
Ordering Information
12
1 Introduction
15
Block Diagram
18
Figure 1: Block Diagram of the Phycard-M
18
View of the Phycard-M
19
Figure 2: Top View of the Phycard-M (Controller Side)
19
Figure 3: Bottom View of the Phycard-M (Connector Side)
20
Minimum Requirements to Operate the Phycard-M
21
2 Pin Description
22
Figure 4: Pin-Out of the Phycard-Connector (Top View, with Cross Section Insert)
23
Table 2: X-Arc Bus Pin-Out
25
Table 3: Pin-Out of the Phycard-Connector X2
29
3 Jumpers
30
Figure 5: Typical Jumper Pad Numbering Scheme
30
Figure 6: Jumper Locations (Top View)
31
Figure 7: Jumper Locations (Bottom View)
32
Table 4: Jumper Settings
34
4 Power
35
Primary System Power (VCC_3V3)
35
Standby Voltage (VBAT)
36
On-Board Voltage Regulator (U1)
36
Figure 8: Power Supply Diagram
37
Supply Voltage for External Logic
38
5 Power Management
39
Table 5: Power Management Pins
39
Table 6: Power States
40
Table 7: Power Management Jumpers J2 and J9
41
6 System Configuration and Booting
42
Table 8: Boot Modes of I.mx35 Module
43
Table 9: Further Boot Configuration Pins
44
7 System Memory
46
Ddr2-Sdram (U8 - U11)
46
NAND Flash Memory (U13)
47
I²C Eeprom (U6)
47
Table 10: Compatible NAND Flash Devices
47
Setting the EEPROM Lower Address Bits (J1, J3, J4).40
48
Table 11: U6 EEPROM I²C Address Via J1, J3, and J4
48
EEPROM Write Protection Control (J16)
49
Memory Model
49
Table 12: EEPROM Write Protection States Via J16
49
8 SD / MMC Card Interfaces
50
Table 13: Location of SD/ MMC Card Interface Signals
50
9 Serial Interfaces
52
Universal Asynchronous Interface
53
Table 14: Location of the UART Signals
53
USB-OTG Interface
54
Table 15: Location of the USB-OTG Signals
54
USB-Host Interface
55
Table 16: Location of the USB-Host Signals
55
Ethernet Interface
56
PHY Physical Layer Transceiver (U7)
56
Table 17: Location of the Ethernet Signals
56
Table 18: Fast Ethernet Controller Memory Map
57
MAC Address
58
C Interface
58
Table 19: I 2 C Interface Signal Location
58
SPI Interface
59
Synchronous Serial Interface (SSI)
59
Table 20: SPI Interface Signal Location
59
Table 21: SSI Interface Signal Location
60
10 General Purpose I/Os
61
Table 22: Location of GPIO and IRQ Pins
61
11 Debug Interface (X1)
62
Figure 9: JTAG Interface at X1 (Top View)
62
Figure 10: JTAG Interface at X1 (Bottom View)
63
Table 23: JTAG Connector X1 Signal Assignment
64
12 LVDS Display Interface
65
Table 24: Display Interface Signal Location
65
LVDS Display Interface Pixel Mapping
66
Signal Configuration (J22)
66
Table 25: Pixel Mapping of 18-Bit LVDS Display Interface
66
Table 26: Pixel Mapping of 24-Bit LVDS Display Interface
67
13 LVDS Camera Interface
68
Signal Configuration (J21)
68
Table 27: Camera Interface Signal Location
68
14 Technical Specifications
69
Figure 11: Physical Dimensions
69
15 Component Placement Diagram
72
Figure 12: Phycard-M Component Placement (Top View)
72
Figure 13: Phycard-M Component Placement (Bottom View)
73
16 Hints for Handling the Phycard-M
74
17 The Phycard-M on the Phybase
75
Concept of the Phybase Board
76
Figure 14: Phybase (Phycard-M Carrier Board)
77
Overview of the Phybase Peripherals
78
Figure 15: Phybase Overview of Connectors, Leds and Buttons
78
Connectors and Pin Header
79
Table 28: Phybase Connectors and Pin Headers
79
Switches
80
Table 29: Phybase Push Buttons Descriptions
80
Table 30: Phybase DIP-Switch S3 Descriptions
83
Leds
84
Table 31: Phybase Leds Descriptions
84
Figure 16: Typical Jumper Numbering Scheme
86
Jumpers
86
Figure 17: Phybase Jumper Locations
87
Table 32: Phybase Jumper Descriptions
89
Functional Components on the Phybase Board
90
Phycard-M SBC Connectivity (X27)
90
Figure 18: Phycard-M SBC Connectivity to the Carrier Board
90
Power Supply (X28)
91
Figure 19: Power Adapter
91
Figure 20: Connecting the Supply Voltage at X28
92
Table 33: Leds Assembled on the Carrier Board
92
Connectivity (P1)
94
Figure 21: UART1 Connection Interface at Connector P1
94
Figure 22: UART1 Connector P1 Signal Description
95
Ethernet Connectivity (X10)
96
Figure 23: Ethernet Interface at Connector X10
96
USB Host Connectivity (X7, X8, X9, X30, X33)
97
Figure 24: USB Host Interface at Connector X7, X30, X33
97
Table 34: Distribution of the USB Hub's (U4) Ports
98
Table 35: Universal USB Pin Header X33 Signal Description
98
USB OTG Connectivity (X29)
99
Figure 25: USB OTG Interface at Connector X29
99
Display / Touch Connectivity (X6, X32)
100
Figure 26: Universal LVDS Interface at Connector X6
100
Display Data Connector (X6)
101
Table 36: Display Data Connector Signal Description
102
Table 37: SPI and GPIO Connector Selection
103
Display Power Connector (X32)
104
Table 38: LVDS Power Connector X32 Signal Description
104
Table 39: Selection of the Touch Screen Controller
105
Touch Screen Connectivity
105
Camera Interface (X5)
107
Table 40: PHYTEC Camera Connector X5
108
Audio Interface (X1,X2,X3)
109
I 2 C Connectivity
110
Table 41: Selection of the Audio Codec
110
Table 42: I 2 C Connectivity
110
Table 43: I C Addresses in Use
111
SPI Connectivity
112
User Programmable Gpios
112
Table 44: SPI Connector Selection
112
Expansion Connectors (X8A, X9A)
113
Table 45: SPI and GPIO Connector Selection
114
Table 46: PHYTEC Expansion Connector X8A, X9A
115
Security Digital Card/ Multimedia Card (X26)
116
Boot Mode Selection (JP1)
117
System Reset Button (S1)
119
RTC at U3
120
PLD at U25
121
Carrier Board Physical Dimensions
122
18 Revision History
123
Index
124
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