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phyCORE-i.MX 6
Phytec phyCORE-i.MX 6 Manuals
Manuals and User Guides for Phytec phyCORE-i.MX 6. We have
1
Phytec phyCORE-i.MX 6 manual available for free PDF download: Hardware Manual
Phytec phyCORE-i.MX 6 Hardware Manual (82 pages)
Brand:
Phytec
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
3
Conventions, Abbreviations and Acronyms
7
Table 1: Signal Types Used in this Manual
8
Table 2: Abbreviations and Acronyms Used in this Manual
9
Preface
10
1 Introduction
15
Features of the Phycore-I.MX 6
15
Block Diagram
17
Figure 1: Block Diagram of the Phycore-I.MX 6
17
Phycore-I.MX 6 Component Placement
18
Figure 2: Phycore-I.MX 6 Component Placement (Top View)
18
Figure 3: Phycore-I.MX 6 Component Placement (Bottom View)
19
Minimum Requirements to Operate the Phycore-I.MX 6
20
2 Pin Description
21
Figure 4: Pinout of the Phycore-Connector (Top View)
22
Table 3: Pinout of the Phycore-Connector X1, Row a
25
Table 4: Pinout of the Phycore-Connector X1, Row B
26
Table 5: Pinout of the Phycore-Connector X1, Row C
28
Table 6: Pinout of the Phycore-Connector X1, Row D
30
3 Jumpers
32
Figure 5: Typical Jumper Pad Numbering Scheme
32
Figure 6: Jumper Locations (Top View)
33
Figure 7: Jumper Locations (Bottom View)
34
Table 7: Jumper Settings
35
4 Power
36
Primary System Power (VDD_3V3)
36
Power Management IC (PMIC) (U16)
36
Power Domains
37
Figure 8: Powering Scheme of the Phycore- I.MX 6
38
Supply Voltage for External Logic
39
Backup Power (PMIC_VBAT/VDD_MX6_SNVS)
39
5 Reset
40
6 System Configuration and Booting
41
Boot Mode Selection
41
Table 8: Boot Modes of the Phycore-I.MX 6
41
Boot Device Selection and Configuration
42
Table 9: Boot Configuration Pins at the Phycore-Connector
43
7 System Memory
44
Ddr3-Sdram (U4-U7)
44
NAND Flash Memory (U12)
45
Emmc Flash Memory (U14)
45
I²C Eeprom (U11)
45
SPI Flash Memory (U9) )
46
EEPROM Write Protection Control (J4)
46
Table 10: EEPROM Write Protection States Via J4
46
8 SD / MM Card Interfaces
47
Table 11: Location of the SD / MM Card Interface Signals
47
9 Serial Interfaces
48
Universal Asynchronous Interface
48
Table 12: Location of the UART Signals
48
USB OTG Interface
49
USB Host Interface
49
Table 13: Location of the USB OTG Signals
49
Table 14: Location of the USB Host Signals
49
Ethernet Interface
50
Ethernet PHY (U2)
50
Table 15: Location of the Ethernet Signals
50
Software Reset of the Ethernet Controller
51
MAC Address
51
RMII Interface
52
Table 16: Location of the RMII Interface Signals
52
SPI Interface
53
Table 17: SPI Interface Signal Location
53
I 2 C Interface
54
I 2 S Audio Interface (SSI))
54
Table 18: I 2 C Interface Signal Location
54
Table 19: I 2 S Interface Signal Location
54
CAN Interface
55
SATA Interface
55
Table 20: CAN Interface Signal Location
55
Table 21: SATA Interface Signal Location
55
PCI Express Interface
56
Table 22: Pcie Interface Signal Location
56
10 General Purpose I/Os
57
Table 23: Location of GPIO Pins
57
11 User LED
58
Figure 9: User LED Location (Top View)
58
12 Debug Interface
59
Table 24: Debug Interface Signal Location at Phycore-Connector X1
59
13 Display Interfaces
60
Parallel Display Interface
60
Table 25: Parallel Display Interface Signal Location
60
LVDS Display Interface
61
Supplementary Signals
61
Table 26: LVDS Display Interface Signal Location
61
Table 27: Supplementary Signals to Support the Display Connectivity
61
14 High-Definition Multimedia Interface (HDMI)
62
Table 28: HDMI Interface Signal Location
62
15 Camera Interfaces
63
Figure 10: Camera Connectivity of the I.MX 6 (Solo/Duallite)
63
Figure 11: Camera Connectivity of the I.MX 6 (Dual Core/Quad Core)
63
Figure 12: Camera Interfaces at the Phycore-Connector (Parallel 0(CSI0 of IPU#1)
64
Parallel 0 Camera Interface (CSI0 of IPU#1)
65
Table 29: Camera Interface Parallel 0 (IPU1_CSI0) Signal Location
65
Parallel 1 Camera Interface (CSI1 of IPU#2)
66
Table 30: Camera Interface Parallel 1 (IPU2_CSI1) Signal Location
66
MIPI/CSI-2 Camera Interface
67
Table 31: Camera Interface MIPI/CSI-2 Signal Location
67
Figure 13: Use of Parallel 0 (CSI0 of IPU#1) and Parallel 1 (CSI1 of IPU#2) as
68
Figure 14: Use of Parallel 0 (CSI0 of IPU#1) and Parallel 1 (CSI1 of IPU#2) as
68
Utilizing the Camera Interfaces on a Carrier Board
68
16 Tamper Detection
69
17 Technical Specifications
70
Figure 15: Physical Dimensions (Top View)
70
Table 32: Technical Specifications
71
Product Temperature Grades
72
Connectors on the Phycore-I.MX 6
73
18 Hints for Integrating and Handling the Phycore-I.MX 6
74
Integrating the Phycore-I.MX 6
74
Figure 16: Footprint of the Phycore-I.MX 6
75
Handling the Phycore-I.MX 6
76
19 Revision History
77
Index
79
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