User Manuals: Nuvoton NuMicro ML51UC0AE Microcontroller

Manuals and User Guides for Nuvoton NuMicro ML51UC0AE Microcontroller. We have 1 Nuvoton NuMicro ML51UC0AE Microcontroller manual available for free PDF download: Technical Reference Manual

Nuvoton NuMicro ML51UC0AE Technical Reference Manual (401 pages)

8-bit Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
General Description
12
Features
14
Part Information
17
3.1 ML51 Series Selection Guide
17
3.2 ML51 Series Selection Code
18
Pin Configuration
19
ML51 Series Pin Diagram
19
Figure 4.1-1 Pin Assignment of QFN-33 Package
19
Figure 4.1-2 Pin Assignment of LQFP-32 Package
20
Figure 4.1-3 Pin Assignment of TSSOP-28 Package
20
Figure 4.1-4 Pin Assignment of SOP-28 Package
21
Figure 4.1-5 Pin Assignment of TSSOP-20 Package
21
Figure 4.1-6 Pin Assignment of TSSOP-20 Package
22
Figure 4.1-7 Pin Assignment of QFN-20 Package
22
Figure 4.1-8 Pin Assignment of TSSOP-14 Package
23
Figure 4.1-9 Pin Assignment of MSOP-10 Package
23
ML51 Series Multi Function Pin Diagram
24
Figure 4.1-10 Multi Function Pin Assignment of QFN-33 Package
24
Figure 4.1-11 Multi Function Pin Assignment of LQFP-32 Package
25
Figure 4.1-12 Multi Function Pin Assignment of TSSOP-28 Package
26
Figure 4.1-13 Multi Function Pin Assignment of SOP-28 Package
26
Figure 4.1-14 Multi Function Pin Assignment of TSSOP-20 Package
26
Figure 4.1-15 Multi Function Pin Assignment of SOP-20 Package
27
Figure 4.1-16 Multi Function Pin Assignment of QFN-20 Package
27
Figure 4.1-17 Multi Function Pin Assignment of Package
28
Figure 4.1-18 Pin Assignment of MSOP-10 Package
28
4.2 Pin Description
29
Block Diagram
37
5.1 Ml51 Full Function Block
37
Figure 5.1-1 Functional Block Diagram
37
Memory Organization
38
6.1 Program Memory
38
6.2 Data Memory
40
Figure 6.1-1 ML51 Program Memory Map
40
Figure 6.2-1 Data Memory Map
40
Figure 6.2-2 Internal 256 Bytes RAM Addressing
42
6.3 On-Chip XRAM
43
6.4 Data Flash
43
Special Function Register (Sfr)
44
Sfr
44
Table 7.1-1 Special Function Register (SFR) Memory Map
45
Table 7.1-2 SFR Definitions and Reset Values
47
7.2 All SFR Description
63
General 80C51 System Control
152
Table 7.2-1 Instructions that Affect Flag Settings
154
O Port Structure and Operation
156
9.1 Quasi-Bidirectional Mode
156
Table 7.2-1 Configuration for Different I/O Modes
156
9.2 Push-Pull Mode
157
Figure 9.1-1 Quasi-Bidirectional Mode Structure
157
Figure 9.2-1 Push-Pull Mode Structure
157
9.3 Input-Only Mode
159
9.4 Open-Drain Mode
159
9.5 Read-Modify-Write Instructions
159
Figure 9.3-1 Input-Only Mode Structure
159
Figure 9.4-1 Open-Drain Mode Structure
159
9.6 Control Registers of I/O Ports
160
Input and Output Data Control
160
GPIO Mode Control
163
GPIO Multi-Function Select
164
Input Type
166
Output Slew Rate Control
167
Pull-Up Resister Control
168
Figure 10.1-1 Timer/Counters 0 and 1 in Mode 0
175
Figure 10.2-1 Timer/Counters 0 and 1 in Mode 1
175
Figure 10.3-1 Timer/Counters 0 and 1 in Mode 2
176
Figure 10.4-1 Timer/Counter 0 in Mode 3
177
Figure 10.4-1 Timer 2 Block Diagram
178
Figure 11.1-1 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram
182
Figure 11.2-1 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram
183
Figure 11.4-1 Timer 3 Block Diagram
189
Figure 13.1-1 WDT as a Time-Out Reset Timer
193
Table 11.4-1 Watchdog Timer-Out Interval under Different Pre-Scalars
193
Figure 13.2-1 Watchdog Timer Block Diagram
194
Figure 13.2-1 Self Wake-Up Timer Block Diagram
196
Figure 15.1-1 Serial Port Mode 0 Timing Diagram
199
Figure 15.2-1 Serial Port Mode 1 Timing Diagram
200
Figure 15.3-1 Serial Port Mode 2 and 3 Timing Diagram
201
Table 15.5-1 Serial Port 0 Mode / Baudrate Description
202
Table 15.5-2 Serial Port 1 Mode / Baudrate Description
203
Figure 16.1-1 SC Controller Block Diagram
216
Figure 16.4-1 SC Data Character
228
Figure 16.4-2 Initial Character TS
229
Figure 16.4-3 SC Error Signal
229
Figure 16.4-4 Transmit Direction Block Guard Time Operation
230
Figure 16.4-5 Receive Direction Block Guard Time Operation
230
Figure 16.4-6 Extra Guard Time Operation
230
Figure 17.1-1 SPI Block Diagram
231
Figure 17.1-2 SPI Multi-Master, Multi-Slave Interconnection
232
Figure 17.1-3 SPI Single-Master, Single-Slave Interconnection
233
Table 17.2-1 Slave Select Pin Configurations
238
Figure 17.4-1 SPI Clock Formats
241
Figure 17.4-2 SPI Clock and Data Format with CPHA = 0
242
Figure 17.4-3 SPI Clock and Data Format with CPHA = 1
242
Figure 17.8-1 SPI Overrun Waveform
244
Figure 17.9-1 SPI Interrupt Request
244
Figure 18.1-1 I 2 C Bus Interconnection
245
Figure 18.1-2 I 2 C Bus Protocol
246
Figure 18.1-3 START, Repeated START, and STOP Conditions
247
Figure 18.1-4 Master Transmits Data to Slave by 7-Bit
247
Figure 18.1-5 Master Reads Data from Slave by 7-Bit
248
Figure 18.1-6 Data Format of One I C Transfer
248
Figure 18.1-7 Acknowledge Bit
249
Figure 18.1-8 Arbitration Procedure of Two Masters
250
Figure 18.1-9 Control I C Bus According to the Current I C Status
251
Figure 18.1-10 Flow and Status of Master Transmitter Mode
252
Figure 18.1-11 Flow and Status of Master Receiver Mode
253
Figure 18.1-12 Flow and Status of Slave Receiver Mode
255
Figure 18.1-13 Flow and Status of General Call Mode
256
Figure 18.4-1 I 2 C Time-Out Counter
267
Figure 18.5-1 Pin Interface Block Diagram
269
Figure 20.1-1 PWM Block Diagram
275
Figure 20.1-2 PWM and Fault Brake Output Control Block Diagram
276
Figure 20.1-3 PWM Edge-Aligned Type Waveform
282
Figure 20.1-4 PWM Center-Aligned Type Waveform
283
Figure 20.1-5 PWM Complementary Mode with Dead-Time Insertion
285
Figure 20.1-6 Fault Brake Function Block Diagram
288
Figure 20.2-1 PWM Interrupt Type
292
Figure 21.1-1 12-Bit ADC Block Diagram
293
Figure 21.1-2 External Triggering ADC Circuit
295
Figure 21.1-3 ADC Result Comparator
296
Figure 21.1-4 ADC Continues Mode with DMA
296
Figure 21.2-1 VREF Block Diagram
304
Figure 21.2-2 Pre-Load Timing
304
Figure 23.1-1 Analog Comparator Block Diagram
306
Figure 23.2-1 Comparator Hysteresis Function
308
Figure 23.3-1 Comparator Reference Voltage Block Diagram
309
Figure 23.4-1 Analog Comparator Interrupt Sources
309
Figure 23.5-1 PDMA Interface Diagram
314
Figure 24.1-1 PDMA Controller Block Diagram
315
Table 26.1-1 Interrupt Vectors
323
Table 26.3-1 Interrupt Priority Level Setting
329
Table 26.3-2 Characteristics of each Interrupt Source
330
Table 27.1-1 IAP Modes and Command Codes
343
Table 27.4-1 Power Mode Table
352
Table 27.4-2 Entry Setting of Power down Mode
352
Figure 28.4-1 Clock System Block Diagram
355
Figure 30.2-1 Brown-Out Detection Block Diagram
362
Table 30.2-1 BOF Reset Value
364
Table 30.2-2 Minimum Brown-Out Detect Pulse Width
366
Figure 31.6-1 Boot Selecting Diagram
371
Table 33.2-1 Instruction Set
380
Figure 36.1-1 CONFIG0 any Reset Reloading
386
Figure 36.3-1 CONFIG2 Power-On Reset Reloading
388
Figure 37.1-1 LQFP-48 Package Dimension
390
Figure 37.2-1 QFN-33 Package Dimension
391
Figure 37.3-1 LQFP-32 Package Dimension
392
Figure 37.4-1 TSSOP-28 Package Dimension
393
Figure 37.5-1 SOP-28 Package Dimension
394
Figure 37.6-1 TSSOP-20 Package Dimension
395
Figure 37.7-1 SOP-20 Package Dimension
396
Figure 37.8-1 QFN-20 Package Dimension
397
Figure 37.9-1 TSSOP-14 Package Dimension
398
Figure 37.10-1 MSOP-10 Package Dimension
399

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User Manuals: Nuvoton NuMicro ML51UC0AE Microcontroller

Nuvoton NuMicro ML51UC0AE Technical Reference Manual (401 pages)

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