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Power control (PWR)
General description
PWR is power management unit to control status of different modules in different power modes. Its major function
is to control MCU to enter different power modes and wakeup when events or interrupts happen. MCU supports
RUN、SLEEP、STOP0、STOP2、STANDBY and VBAT mode.
4.1.1 Power supply
MCU working voltage (VDD) is 1.8V~3.6V. It mainly has 3 analog/digital power supply regions (VDD, VBAT,
VDDA). For details, please refer to Figure 4-1 power supply block diagram. In order to illustrate the functions
of different power domains, some power domains will be introduced below, and the digital parts of power
domains will be introduced in later chapters of this document.
V
domain: The voltage input range is 1.8V~3.6V, mainly for MR,CPU,AHB,APB,SRAM,FLASH and
DD
most digital peripheral interfaces power supply.
VBAT domain: The input voltage range is 1.8V~3.6V, which supplies power for BKR and some special IO
(PC13, PC14, PC15) ports. When VDD is powered down, the switch switches the power supply system
VDD to VBAT.
VDDA domain: voltage input range is 1.8V~3.6V, mainly used for clock and reset system, most analog
peripherals powered.
BKR and MR are internal voltage regulators that can provide power for the digital module power supply system.
VDD and VBAT are generally powered directly from the outside, VBAT is powered by the battery to keep the
contents of the backup area, and VDD is powered by other external power supply systems. In addition, if no
battery is required, then VBAT must be connected directly to VDD.
MR
MR is the internal main power controller, mainly used in RUN mode, SLEEP mode and STOP0 mode. MR
has two modes, normal mode and low power mode, the low power mode is used for STOP0 to further
reduce power consumption.
When the MR enters a low power mode, the CPU goes into a deep sleep state. In this case, the
PWR_CTRL.PDS bit should be set to 0 and the PWR_CTRL.LPS bit should be set to 1. When the MR
enters the normal mode, the PWR_CTRL.PDS bit needs to be set to 0, and the PWR_CTRL.LPS bit is also
0.
BKR
BKR is an internal backup domain power controller, used in STOP2, STANDBY and VBAT modes. In
STOP2 mode, the CPU state is maintained and additionally supplies power to the digital backup area, GPIO
and EXTI. When the CPU enters deep sleep, the PWR_CTRL2.STOP2S bit should be set to 1 at this time.
The main modules of the digital backup area include PWR, IO (PA0_WAKUP, PC13_TAMPER, PC14,
PC15), R-SRAM, RTC, BKR and RCC_BDCTRL registers. When the SW3 switch is on, the CPU goes
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