Figure 21-25 I 2 S Clock Generator Structure; Figure 21-26 Audio Sampling Frequency Definition - Nations N32G45 Series User Manual

MCLK
0
1
CLK
MCLKOEN
- -
Note: The clock source of I
The bit rate of I2S determines the data flow on the I2S data line and the frequency of the I2S clock signal.
2
I S bit rate = number of bits per channel × number of channels × audio sampling frequency
For a signal with left and right channels and 16-bit audio, the I2S bit rate is calculated as:
If the packet length is 32 bits, there are:
The sampling signal frequency of the audio can be set by setting the SPI_I2SPREDIV.ODD_EVEN bit and the
SPI_I2SPREDIV.LDIV[7:0] bits. Audio can be sampled at 96kHz, 48kHz, 44.1kHz, 32kHz, 22.05kHz, 16kHz,
11.025kHz, or 8kHz (or any value within this range). Set the linear divider according to the following formula:
When MCLKOEN = 1 and CHBITS= 0, ��
When MCLKOEN = 1 and CHBITS = 1, ��
When MCLKOEN = 0 and CHBITS = 0, ��
When MCLKOEN = 0 and CHBITS = 1, ��
The exact audio frequency can be obtained by referring to the clock configuration in the table below.
Figure 21-25 I
Divider
0
by 2
1
MOD
- - - -
SEL
2
Sx CLK is HSI, HSE or PLL system clock that drives AHB clock.
2
I S bit rate = 16 × 2 × F
2
I S bit rate = 32 × 2 × F

Figure 21-26 Audio sampling frequency definition

2
= �� ���� ������ [ ( 16 × 2 ) × ( ( 2 × �������� ) + ������_��������) × 8]
��
2
���� ������ [ ( 32 × 2 ) × ( ( 2 × �������� ) + ������_��������) × 4]
= ��
��
2
= �� ���� ������ [ ( 16 × 2 ) × ( ( 2 × �������� ) + ������_��������)]
��
2
= �� ���� ������ [ ( 32 × 2 ) × ( ( 2 × �������� ) + ������_��������)]
��
2
S clock generator structure
Divider
by 4
MCLK ODD_
I2SEN
OEN EVEN
S
S
⁄
⁄
⁄
⁄
593 / 838
8-bit Linear
Divider +
reshaping
stage
LDIV[7:0]
Nations Technologies Inc.
Tel：+86-755-86309900
Email：info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
I2Sx CLK