Eth Mac Interrupt Mask Register (Eth_Macintmsk); Eth Mac Address 0 High Register (Eth_Macaddr0Hi) - Nations N32G45 Series User Manual

Bit field Name
2:0 Reserved

25.5.13 ETH MAC interrupt mask register (ETH_MACINTMSK)

Address offset: 0x003C
Reset value: 0x0000 0000
Bit field Name
31:10 Reserved
9 TSIM
8:4 Reserved
3 PMTIM
2:0 Reserved

25.5.14 ETH MAC address 0 high register (ETH_MACADDR0HI)

Address offset: 0x0040
Reset value: 0x8000 FFFF
Description
In low power mode, this bit is set to 1 when a remote wakeup frame or Magic Packet
wakeup frame is received. This bit is also cleared to 0 after clearing
ETH_MACPMTCTRLSTS.RWKPRCVD and
ETH_MACPMTCTRLSTS.MGKPRCVD by reading the ETH_MACPMTCTRLSTS
register.
Reserved, the reset value must be maintained.
Description
Reserved, the reset value must be maintained.
Timestamp trigger interrupt mask bit.
0: Enable generation of timestamp interrupts.
1: Disable generation of timestamp interrupts.
Reserved, the reset value must be maintained.
PMT interrupt mask bit.
0: Enable generation of interrupts caused by ETH_MACINTSTS.PMTIS being set to
1.
1: Disable generation of interrupts caused by ETH_MACINTSTS.PMTIS being set to
1.
Reserved, the reset value must be maintained.
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