Maxim Integrated MAX32660 Manuals

Manuals and User Guides for Maxim Integrated MAX32660. We have 1 Maxim Integrated MAX32660 manual available for free PDF download: User Manual

Maxim Integrated MAX32660 User Manual (195 pages)

Brand: Maxim Integrated | Category: Microcontrollers | Size: 4 MB

Table of Contents
8
Introduction
13
Overview
13
Figure 2-1: MAX32660 High Level Block Diagram
14
Figure 3-1: Code Memory Mapping
15
Memory, Register Mapping, and Access
15
Figure 3-2: Data Memory Map
16
Table 3-1: APB Peripheral Base Address Map
19
Table 4-1: Operating Voltage Range Selection and the Effect on V
21
System Clocks, Reset, and Power Management
21
Table 4-2: Minimum Flash Wait State Setting for each OVR Setting
23
Figure 4-1: Clock Tree Diagram
24
Table 4-3: Reset Sources and Effect on Oscillator Status
25
Table 4-4: Reset Sources and Effect on System Oscillator Selection and Prescaler
25
Table 4-5: Wake-Up Sources for each Low-Power Mode
28
Table 4-6: Reset and Low Power Mode Effects
29
Table 4-7: Instruction Cache Controller Register Addresses and Descriptions
31
Table 4-8: ICC Cache ID Register
31
Table 4-9: ICC Memory Size Register
31
Table 4-10: ICC Cache Control Register
32
Table 4-11: ICC Invalidate Register
32
Table 4-12: Global Control Registers, Offsets and Descriptions
33
Table 4-13: System Control Register
33
Table 4-14: Reset 0 Register
34
Table 4-15: System Clock Control Register
36
Table 4-16: Power Management Register
38
Table 4-17: Peripheral Clock Disable 0 Register
38
Table 4-18: Memory Clock Control Register
40
Table 4-19: Memory Zeroization Control Register
42
Table 4-20: System Status Flag Register
42
Table 4-21: Reset Register 1
43
Table 4-22: Peripheral Clock Disable Register 1
43
Table 4-23: Event Enable Register
44
Table 4-24: Revision Register
44
Table 4-25: System Status Interrupt Enable Register
44
Table 4-26: System Initialization Registers, Offsets and Descriptions
44
Table 4-27: Function Control Register 0
45
Table 4-28: System Initialization Address Error Register
45
Table 4-29: Function Control Registers, Offsets and Descriptions
45
Table 4-30: Function Control Register 0
45
Table 4-31: Power Sequencer Low Power Control Registers, Offsets, Access and Descriptions
46
Table 4-32: Low Power Voltage Control Register
47
Table 4-33: Low Power Mode Wakeup Flags for GPIO0
49
Table 4-34: Low Power Wakeup Enable for GPIO0 Register
49
Table 4-35: RAM Shut down Register
49
Table 5-1: Internal Flash Memory Organization
51
Table 5-2: Valid Addresses for 32-Bit and 128-Bit Internal Flash Writes
52
Table 5-3: Page Boundary Address Range for Page Erase Operations
53
Table 5-4: Flash Controller Registers, Offsets, Access and Descriptions
54
Table 5-5: Flash Controller Interrupt Register
56
Table 5-6: Flash Controller Data Register 0
57
Table 5-7: Flash Controller Data Register 1
57
Table 5-8: Flash Controller Data Register 2
57
Table 5-9: Flash Controller Data Register 3
57
Table 6-2: GPIO Port, Pin Name and Alternate Function Matrix, 20-TQFN
59
Table 6-1: GPIO Port, Pin Name and Alternate Function Matrix, 16-WLP
59
Table 6-3: Standard GPIO Drive Strength Selection
61
Table 6-4: GPIO with I 2 C Alternate Function Drive Strength Selection
61
Table 6-5: GPIO Mode and Alternate Function Selection
61
Table 6-6: GPIO Port Interrupt Vector Mapping
62
Table 6-7: GPIO Wakeup Interrupt Vector
62
Table 6-8: GPIO Port 0 Registers
63
Table 6-9: GPIO Alternate Function 0 Select Register
63
Table 6-10: GPIO Output Enable Register
64
Table 6-11: GPIO Output Register
64
Table 6-12: GPIO Input Register
65
Table 6-13: GPIO Port Interrupt Mode Register
65
Table 6-14: GPIO Port Interrupt Polarity Registers
65
Table 6-15: GPIO Port Interrupt Enable Registers
65
Table 6-16: GPIO Interrupt Flag Register
66
Table 6-17: GPIO Wakeup Enable Registers
66
Table 6-18: GPIO Interrupt Dual Edge Mode Registers
66
Table 6-19: GPIO Pullup/Pulldown Enable Register
67
Table 6-20: GPIO Alternate Function Select Register
67
Table 6-21: GPIO Input Hysteresis Enable Register
67
Table 6-22: GPIO Slew Rate Enable Register
67
Table 6-23: GPIO Drive Strength 0 Select Register
68
Table 6-24: GPIO Drive Strength 1 Select Register
69
Table 6-25: GPIO Pullup/Pulldown Select Register
70
Figure 7-1: DMAC Block Diagram
71
Table 7-1: DMA Channel Registers
71
Table 7-2: Channel Reload Registers
72
Table 7-3: Source and Destination Address Definition
73
Table 7-4: Data Movement from Source to DMA FIFO
73
Table 7-5: Data Movement from the DMA FIFO to Destination
74
Table 7-6: Standard DMA Control Registers, Offsets, Access and Descriptions
77
Table 7-7: DMA Interrupt Enable Register
77
Table 7-8: DMA Interrupt Flag Register
77
Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets
78
Table 7-10: Dman Channel Registers, Offsets, Access and Descriptions
78
Table 7-11: DMA Configuration Register
79
Table 7-12: DMA Status Register
81
Table 7-13: DMA Source Register
82
Table 7-14: DMA Destination Register
82
Table 7-15: DMA Count Register
82
Table 7-16: DMA Source Reload Register
83
Table 7-17: DMA Destination Reload Register
83
Table 7-18: DMA Count Reload Register
83
Table 8-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps, F
86
Table 8-2: UART Registers, Offset Addresses and Descriptions
87
Table 8-3: UART Control 0 Register
87
Table 8-4: UART Control 1 Register
89
Table 8-5: UART Status Register
90
Table 8-6: UART Interrupt Enable Register
91
Table 8-7: UART Interrupt Flags Register
92
Table 8-8: UART Rate Integer Register
93
Table 8-9: UART Baud Rate Decimal Register
93
Table 8-10: UART FIFO Register
94
Table 8-11: UART DMA Configuration Register
94
Table 8-12: UART TX FIFO Data Output Register
94
Figure 9-1. RTC Block Diagram
97
Table 9-1. RTC Registers, Offsets and Descriptions
100
Table 9-2: RTC Seconds Counter Register
100
Table 9-3: RTC Sub-Seconds Counter Register
101
Table 9-4: RTC Sub-Seconds Counter Register
101
Table 9-5: RTC Sub-Second Alarm Register
101
Table 9-6: RTC Control Register
101
Table 9-7: RTC Trim Register
103
Figure 10-1: One-Shot Mode Diagram
107
Figure 10-2: Continuous Mode Diagram
109
Figure 10-3: Counter Mode Diagram
111
Figure 10-4: Capture Mode Diagram
115
Figure 10-5: Counter Mode Diagram
117
Figure 10-6: Gated Mode Diagram
119
Table 10-1: Timer Register Offsets, Names, Access and Descriptions
122
Table 10-2: Timer Count Registers
122
Table 10-3: Timer Compare Registers
122
Table 10-4: Timer PWM Registers
123
Table 10-5: Timer Interrupt Registers
123
Table 10-6: Timer Control Registers
123
Figure 11-1: Watchdog Timer Block Diagram
126
Table 11-1: Watchdog Timer Interrupt Period with F
127
Table 11-2: Watchdog Timer Registers
129
Table 11-3: Watchdog Timer Control Register
129
Table 11-4: Watchdog Timer Reset Register
130
Table 12-1: I 2 C Bus Terminology
131
Figure 12-1: the Roles of I C Devices and the Direction the I C Signals
132
Figure 12-2: I C Write Data Transfer
134
Figure 12-3: I C Specification Minimum and Maximum Clock Parameters for Standard and Fast Mode
136
Table 12-2: I C Address Byte Format
138
Figure 12-4: I C Clock Period
142
Table 12-3: I C Registers
144
Table 12-4: I 2 C Control Registers 0
145
Table 12-5: I C Status Registers
147
Table 12-6: I 2 C Interrupt Status Flags Registers 0
148
Table 12-7: I C Interrupt Enable 0 Registers
150
Table 12-8: I C Interrupt Status Flags 1 Registers
151
Table 12-9: I 2 C Interrupt Enable Registers 1
151
Table 12-10: I C FIFO Length Registers
152
Table 12-11: I 2 C Receive Control Registers 0
152
Table 12-12: I C Receive Control 1 Registers
153
Table 12-13: I 2 C Transmit Control Registers 0
153
Table 12-14: I 2 C Transmit Control Registers 1
154
Table 12-15: I C Data Registers
155
Table 12-16: I C Master Mode Control Registers
155
Table 12-17: I C SCL Low Control Register
156
Table 12-18: I C SCL High Control Register
156
Table 12-19: I C Timeout Registers
156
Table 12-20: I C Timeout Registers
157
Table 12-21: I C Slave Address Register
157
Table 12-22: I C DMA Register
158
Figure 13-1: SPI0 Block Diagram
159
Figure 13-2: 4-Wire SPI Connection Diagram
160
Table 13-1: Four-Wire SPI Signals
160
Figure 13-3: 3-Wire SPI Connection Diagram
161
Table 13-2: Three-Wire SPI Signals
161
Table 13-3: SPI0 Pins
162
Figure 13-4: SCK Clock Rate Control
163
Table 13-4. Clock Phase and Polarity Operation
164
Figure 13-5: SPI Clock Polarity
164
Figure 13-6. SPI Timing (Spi0_Ctrl2.Clk_Pha = 0)
165
Figure 13-7. SPI Timing (Spi0_Ctrl2.Clk_Pha = 1)
166
Figure 13-8: Three-Wire SPI Read
167
Figure 13-9: Three-Wire SPI Write
167
Table 13-5: SPI0 Master Register Addresses and Descriptions
169
Table 13-6: SPI FIFO Data Registers
169
Table 13-7: SPI Master Signals Control Registers
169
Table 13-8: SPI Transmit Packet Size Register
171
Table 13-9: SPI Static Configuration Registers
171
Table 13-10: SPI Slave Select Timing Register
172
Table 13-11: SPI Master Clock Configuration Registers
172
Table 13-12: SPI DMA Control Registers
173
Table 13-13: SPI Interrupt Flag Registers
174
Table 13-14: SPI Interrupt Enable Registers
176
Table 13-15: SPI Wakeup Status Flags Registers
177
Table 13-16: SPI Wakeup Enable Registers
177
Table 13-17: SPI Status Registers
177
Table 14-1: Four-Wire SPI Signals
179
Figure 14-1. SPIMSS Block Diagram
179
Table 14-2: I S Signals
180
Figure 14-2: 4-Wire SPI Connection Diagram
180
Table 14-3: SPIMSS Pins for SPI1 and I 2 S
181
Table 14-4. Clock Phase and Polarity Operation
182
Figure 14-3: I S Audio Data in Standard I S Operation
186
Figure 14-4: I S Mode (I2S_En=1, I2S_Lj=1)
186
Table 14-5: SPIMSS Register Offsets, Access and Descriptions
189
Table 14-6. SPIMSS Data Register
189
Table 14-7: SPIMSS Control Register
189
Table 14-8: SPIMSS Interrupt Flag Register
190
Table 14-9: SPIMSS Mode Register
191
Table 14-10: SPIMSS Bit Rate Generator Register
192
Table 14-11: SPIMSS DMA Register
192
Table 14-12: SPIMSS I 2 S Control Register
194

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