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IDT Tsi350A Manuals
Manuals and User Guides for IDT Tsi350A. We have
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IDT Tsi350A manual available for free PDF download: User Manual
IDT Tsi350A User Manual (180 pages)
PCI-to-PCI Bridge
Brand:
IDT
| Category:
Recording Equipment
| Size: 0.98 MB
Table of Contents
About this Document
3
Scope
3
Document Conventions
3
Revision History
4
Table of Contents
7
1 Functional Overview
17
Overview of the Tsi350A
17
Figure 1: Block Diagram
18
Features
19
Figure 2: System Block Diagram
19
Compliance
20
Functional Description
20
PCI Interface
20
JTAG Controller
21
Hot Swap Interface
21
Architecture
22
Data Path
22
Posted Write Queue
23
Delayed Transaction Queue
23
Figure 3: Tsi350A Downstream Data Path
23
Read Data Queue
24
2 PCI Interface
25
Transaction Types
25
Table 1: Tsi350A PCI Transactions
26
Transaction Phases
27
Address Phase
27
Data Phase
28
Write Transactions
28
Posted Write Transactions
28
Memory Write and Invalidate Transactions
29
Delayed Write Transactions
30
Write Transaction Address Boundaries
31
Buffering Multiple Write Transactions
31
Table 2: Write Transaction Address Boundaries
31
Read Transactions
32
Table 3: Read Transaction Prefetching
32
Calculating the Prefetch Count
33
Non-Prefetchable Read Transactions
34
Prefetchable Read Transactions
34
Read Prefetch Address Boundaries
34
Delayed Read Requests
35
Table 4: Read Prefetch Address Boundaries
35
Configuration Transactions
37
Figure 4: Type 0 Configuration Transaction
37
Figure 5: Type 1 Configuration Transaction
37
Type 0 Access to Tsi350A
38
Type 1 to Type 0 Translation
38
Table 5: Device Number to IDSEL S_AD Pin Mapping
39
Type 1 to Type 1 Forwarding
41
Transaction Termination
42
Master Termination Initiated by Tsi350A
43
Master Abort Received by Tsi350A
43
Target Termination Received by Tsi350A
44
Table 6: Tsi350A Response to Delayed Write Transaction
44
Table 7: Tsi350A Response to Posted Write Termination
45
Target Termination Initiated by Tsi350A
46
Table 8: Tsi350A Response to Delayed Read Target Termination
46
3 Address Decoding
49
Overview of Address Decoding
49
Address Ranges
49
Base and Limit Address Registers
50
ISA Mode
51
Memory Address Decoding
51
Memory-Mapped I/O Base and Limit Address Registers
52
Prefetchable Memory Base and Limit Address Registers
53
Prefetchable Memory 64-Bit Addressing Registers
54
VGA Support
55
VGA Mode
55
VGA Snoop Mode
56
4 Transaction Ordering
57
Transaction Governed by Ordering Rules
57
General Ordering Guidelines
58
Ordering Rules
59
Table 9: Summary of Transaction Ordering
59
5 Error Handling
61
Address Parity Errors
61
Data Parity Errors
62
Configuration Write Transactions to Tsi350A Configuration Space
62
Read Transactions
62
Delayed Write Transactions
63
Posted Write Transactions
65
System Error (Serr_B) Reporting
66
6 Exclusive Access
69
Concurrent Locks
69
Acquiring Exclusive Access Across the Tsi350A
69
Ending Exclusive Access
70
7 PCI Bus Arbitration
73
Overview
73
Primary PCI Bus Arbitration
73
Secondary PCI Bus Arbitration
74
Secondary Bus Arbitration Using the Internal Arbiter
74
Secondary Bus Arbitration Using an External Arbiter
75
Bus Parking
75
8 General Purpose I/O
77
Overview
77
GPIO Control Registers
77
Secondary Clock Control
78
Figure 6: Clock Mask Load and Shift Timing
79
Table 10: Clock Mask Data Format
79
Live Insertion
80
Compactpci Hot-Swap Support
80
Table 11: Tsi350A Hot-Swap Mode Selection
81
9 Clocks
83
Overview
83
Primary and Secondary Clock Inputs
83
Synchronous Secondary Clock Input
83
Asynchronous Secondary Clock Input
83
Secondary Clock Outputs
84
Running the Secondary Clock Faster than the Primary Clock
84
Table 12: Tsi350A S_CLK_O Clock Outputs
84
10 PCI Power Management
85
Table 13: Power Management Transitions
85
11 Reset
87
Primary Interface Reset
87
Secondary Interface Reset
87
Chip Reset
88
12 JTAG Module
89
JTAG Signal Pins
89
Table 14: JTAG Signal Pins
89
Test Access Port (TAP) Controller
90
Instruction Register
90
Bypass Register
90
Table 15: JTAG Instructions
90
Boundary-Scan Register
91
Initialization
91
13 Signals and Pinout
93
Table 16: Tsi350A Signal Pins
93
Table 17: Tsi350A Signal Types
94
Signals
95
Primary PCI Bus Interface Signals
95
Table 18: Primary PCI Bus Interface Signals
95
Secondary PCI Bus Interface Signals
97
Table 19: Secondary PCI Bus Interface Signals
97
Secondary Bus Arbitration Signals
99
Table 20: Secondary PCI Bus Arbitration Signals
99
Clock Signals
100
Table 21: Clock Signals
100
Reset Signals
101
Miscellaneous Signals
101
Table 22: Tsi350A Reset Signals
101
Table 23: Tsi350A Miscellaneous Signals
101
JTAG Signals
103
Power and Ground Pins
103
Table 24: JTAG Signals
103
Table 25: Power and Ground Pins
103
Pinout
104
208-Pin PQFP Pin List
104
Table 26: Tsi350A 208 Pin List
104
256-Pin PBGA Pin List
112
Table 27: Tsi350A 256 Pin List
112
Table 28: Tsi350A 256 Pin List - Power, Ground, and Reserved
117
14 Electrical Characteristics
119
Absolute Maximum Ratings
119
Recommended Operating Conditions
119
Table 29: Absolute Maximum Ratings
119
Table 30: Recommended Operating Conditions
119
Power Characteristics
120
Power Supply Sequencing
120
DC Specifications
120
Table 31: Power Characteristics
120
Table 32: Tsi350A DC Specifications
120
AC Timing Specifications
122
Figure 7: PCI Signal Timing Measurement Conditions
122
Table 33: 33 Mhz PCI Signal Timing
123
Table 34: 66 Mhz PCI Signal Timing
123
15 Registers
125
Table 35: Tsi350A Configuration Space
125
Reserved Register Addresses and Fields
127
Table 36: Register Access Types
127
PCI-To-PCI Bridge Standard Configuration Registers
128
Vendor ID Register-Offset 0X00
128
Device ID Register-Offset 0X00
128
Primary Command Register-Offset 0X04
129
Primary Status Register-Offset 0X04
131
Revision ID Register-Offset 0X08
133
Programming Interface Register-Offset 0X08
133
Subclass Code Register-Offset 0X08
133
Base Class Code Register-Offset 0X08
134
Cache Line Size Register-Offset 0X0C
135
Primary Latency Timer Register-Offset 0X0C
135
Header Type Register-Offset 0X0C
135
Primary Bus Number Register-Offset 0X18
136
Secondary Bus Number Register-Offset 0X18
136
Subordinate Bus Number Register-Offset 0X18
137
Secondary Latency Timer Register-Offset 0X18
137
I/O Base Address Register-Offset 0X1C
138
I/O Limit Address Register-Offset 0X1C
138
Secondary Status Register-Offset 0X1C
139
Memory Base Address Register-Offset 0X20
141
Memory Limit Address Register-Offset 0X20
141
Prefetchable Memory Base Address Register-Offset 0X24
142
Prefetchable Memory Limit Address Register-Offset 0X24
142
Prefetchable Memory Base Address Upper 32 Bits Register-Offset 0X28
143
Prefetchable Memory Limit Address Upper 32 Bits Register-Offset 0X2C
144
I/O Base Address Upper 16 Bits Register-Offset 0X30
145
I/O Limit Address Upper 16 Bits Register-Offset 0X30
145
ECP Pointer Register-Offset 0X34
146
Interrupt Pin Register-Offset 0X3C
146
Bridge Control Register-Offset 0X3C
147
Device-Specific Configuration Registers
151
Chip Control Register-Offset 0X40
152
Diagnostic Control Register-Offset 0X40
153
Arbiter Control Register-Offset 0X40
154
Read Transaction Control Register- Offset 0X44
155
P_Serr_B Event Disable Register-Offset 0X64
156
GPIO Output Data Register-Offset 0X64
157
GPIO Output Enable Control Register-Offset 0X64
158
GPIO Input Data Register-Offset 0X64
158
Secondary Clock Control Register-Offset 0X68
159
P_Serr_B Status Register-Offset 0X68
160
Capability ID Register-Offset 0Xdc
161
Next Item Pointer Register-Offset 0Xdd
161
Power Management Capabilities Register-Offset 0Xde
162
Power Management Control and Status Register-Offset 0Xe0
163
PPB Support Extensions Registers-Offset 0Xe2
164
Data Register-Offset 0Xe3
164
HS Capability ID Register- Offset 0Xe4
165
HS Next Item Pointer Register- Offset 0Xe5
165
HS Control Status Register- Offset 0Xe6
166
Package Information
169
Package Characteristics
169
208-Pin PQFP Package
169
Table 37: PQFP Symbol Values
169
Figure 8: 208-Pin PQFP Package Diagram - Top View
170
Figure 9: 208-Pin PQFP Package Diagram - Side View
171
Figure 10: 208-Pin PQFP Package Diagram - Side View
171
256-Pin PBGA Package
172
Figure 11: 256-Pin PBGA Package Diagram - Top View
172
Figure 12: 256-Pin PBGA Package Diagram - Bottom View
173
Figure 13: 256-Pin PBGA Package Diagram - Side View
173
Thermal Characteristics
174
Junction-To-Ambient Thermal Characteristics (Theta Ja)
174
Table 38: Thermal Characteristics of the Tsi350A
174
Table 39: Simulated Junction to Ambient Characteristics
174
A.2 Thermal Characteristics
174
System-Level Characteristics
175
Example on Thermal Data Usage
175
Ordering Information
177
Table 40: Ordering Information
177
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