IDT TSI384 Manuals

Manuals and User Guides for IDT TSI384. We have 1 IDT TSI384 manual available for free PDF download: User Manual

IDT TSI384 User Manual

IDT TSI384 User Manual (281 pages)

PCIe-to-PCI Bridge

Brand: IDT | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
3
About this Document

15
- Scope
  15
- Document Conventions
  15
- Revision History
  17
1 Functional Overview

19
- Overview
  19
- Features
  20
  - General Features
    20
  - Figure 1: Tsi384 Block Diagram
    20
  - Pcie Features
    21
  - PCI-X Features
    21
  - PCI Features
    21
- Device Architecture
  22
- Figure 2: Tsi384 Device Architecture
  22
- Typical Applications
  25
- Figure 3: Motherboard Application - PC, Server, SBC, Industrial PC
  25
- Figure 4: External Storage Application
  26
- Figure 5: Server Add-In Cards for Networking and Storage
  26
2 Signal Descriptions

27
- Overview
  27
- Table 1: Pin Types
  27
- Pcie Interface Signals
  28
- Table 2: Pcie Interface Signals
  28
- PCI/X Interface Signals
  29
- Table 3: PCI/X Interface Signals
  29
- EEPROM Interface Signals
  32
- Table 4: EEPROM Interface Signals
  32
- JTAG Interface Signals
  33
- Table 5: JTAG Interface Signals
  33
- Power-Up Signals
  34
- Power Supply Signals
  34
- Table 6: Power-Up Signals
  34
- Table 7: Power Supply Signals
  34
3 Data Path

37
- Overview
  37
  - Upstream Data Path
    37
  - Downstream Data Path
    38
  - Figure 6: Upstream Data Path
    38
- Transaction Management
  39
- Buffer Structure
  40
  - Upstream Non-Posted Buffer
    40
  - Upstream Posted Buffer
    41
  - Downstream Non-Posted Buffer
    42
  - Downstream Posted Buffer
    42
- Flow Control
  42
- Prefetching Algorithm
  43
- Table 8: Initial Credit Advertisement
  43
- Short Term Caching
  44
- Lane Reversal and Polarity Reversal
  44
4 Addressing

45
5 Configuration Transactions

57
6 Bridging

63
- Overview
  63
- Flow Control Advertisements
  63
- Buffer Size and Management
  64
- Assignment of Requestor ID and Tag
  64
- Forwarding of Pcie to PCI
  65
  - Pcie Memory Write Request
    65
  - Pcie Non-Posted Requests
    65
- Forwarding of Pcie to PCI-X
  66
  - Pcie Memory Write Request
    66
  - Pcie Non-Posted Requests
    66
- Forwarding of PCI to Pcie
  67
  - PCI Memory Write Request
    67
  - PCI Non-Posted Requests
    67
- Forwarding of PCI-X to Pcie
  68
- Split Completion Buffer
  68
- PCI Transaction Support
  69
- Table 9: PCI Transaction Support
  69
- PCI-X Transaction Support
  70
- Table 10: PCI-X Transaction Support
  70
- Pcie Transaction Support
  71
- Table 11: Pcie Transaction Support
  71
- Message Transactions
  72
  - Intx Interrupt Signaling
    72
  - Power Management
    72
  - Locked Transaction
    72
  - Slot Power Limit
    72
  - Vendor-Defined and Device ID
    72
- Transaction Ordering
  73
- Table 12: Transaction Ordering
  73
7 PCI/X Arbitration

75
- Overview
  75
- Block Diagram
  75
- PCI/X Arbitration Scheme
  76
- Figure 18: PCI/X Arbiter Block Diagram
  76
- Figure 19: PCI/X Arbitration Priority
  77
8 Interrupt Handling

79
- Overview
  79
- Interrupt Sources
  80
- Interrupt Routing
  80
- Figure 20: Interrupt Handling Diagram
  80
9 Error Handling

81
10 Reset, Clocking, and Initialization

111
- Reset
  111
  - Table 26: Reset Summary
    111
  - Figure 24: Reset Timing
    112
  - Pcie Link Reset
    112
  - Table 27: Reset Timing
    112
  - PCI/X Bus Reset
    113
- Clocking
  114
  - Pcie Clocking
    114
  - PCI/X Clocking
    114
  - Figure 25: Pcie Clocking
    114
  - Figure 26: PCI/X Clocking
    115
  - Figure 27: Master Mode Clocking
    116
  - Table 28: PCI/X Bus Mode and Speed Capability
    116
  - Table 29: Master Mode and Clock Rate
    117
  - Table 30: Master Mode External Clock Compensation
    117
  - Figure 28: Slave Clocking
    118
- Initialization
  119
- Table 31: Slave Mode and Clock Rate
  119
- Table 32: Slave Mode Clock Insertion Compensation
  119
- Table 33: Initialization Pattern
  120
11 Power Management

121
- Overview
  121
  - Features
    121
  - Unsupported Features
    122
- Power Management Capabilities
  122
- Power States
  122
  - Aspm
    122
  - L0 State
    123
  - L0S State
    123
  - L1 State
    123
  - L2/L3 Ready
    123
  - L3 State
    123
  - Ldn State
    123
  - Link State Summary
    124
  - Figure 29: Pcie Link Power Management States
    124
  - Table 34: Pcie Link States
    124
  - Device Power States
    125
  - D0 State
    125
  - D3 Hot State
    125
  - D3 Cold State
    125
  - D State Transitions
    126
  - Power Management Event
    126
  - Figure 30: D State Transitions
    126
  - Power State Summary
    127
  - Table 35: Power Management State Summary
    127
12 Serial EEPROM

129
- Overview
  129
- System Diagram
  130
- Figure 31: EEPROM Interface
  130
- EEPROM Image
  132
- Table 36: EEPROM Image
  132
- Functional Timing
  133
- Figure 32: 9-Bit EEPROM Read Timing
  133
- Figure 33: 16-Bit EEPROM Read Timing
  134
- Figure 34: 9-Bit EEPROM Write Timing
  134
- Figure 35: 16-Bit EEPROM Write Timing
  135
- Figure 36: EEPROM WREN Instruction Timing
  135
- Figure 37: EEPROM RDSR Instruction Timing
  135
13 Jtag

137
- Overview
  137
- TAP Controller Initialization
  138
- Instruction Register
  138
- Bypass Register
  138
- JTAG Device ID Register
  138
- JTAG Register Access
  139
- Dedicated Test Pins
  141
- Accessing Serdes TAP Controller
  141
- Figure 40: Pcie Serdes Connections
  141
14 Register Descriptions

143
15 Electrical Characteristics

247
16 Packaging

265
- Mechanical Diagram
  265
- Figure 49: Mechanical Diagram 256 Pin 17X17Mm BGA
  265
- Thermal Characteristics
  266
- Table 57: Thermal Characteristics
  266
- Table 58: Junction to Ambient Characteristics
  266
- Moisture Sensitivity
  267
17 Ordering Information

269
- Part Numbers
  269
- Part Numbering Information
  269
- Table 59: Part Numbers
  269
Pcie Programmable Transmit and Receive Equalization

271
- Overview
  271
- Transmit Drive Level and Equalization
  271
- Receive Equalization
  272
- Figure 50: Drive Strength and Equalization Waveform
  272
- A.3 Receive Equalization
  272
Glossary

273
Index

277

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