User Manuals: Artesyn MVME5100 VME Embedded Controller

User Manuals: Artesyn MVME5100 VME Embedded Controller

Manuals and User Guides for Artesyn MVME5100 VME Embedded Controller. We have 1 Artesyn MVME5100 VME Embedded Controller manual available for free PDF download: Programmer's Reference Manual

Artesyn MVME5100 Programmer's Reference Manual

Artesyn MVME5100 Programmer's Reference Manual (318 pages)

Brand: Artesyn | Category: Motherboard | Size: 20 MB

Table of Contents

Table of Contents
3
List of Figures
16
About this Manual

17
- Summary of Changes
  24
1 Product Data and Memory Maps

25
2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

63
- Overview
  63
  - Features
    63
  - Table 2-1 2Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
    63
- Block Diagram
  65
- Figure 2-1 Hawk PCI Host Bridge Block Diagram
  65
- Functional Description
  66
- Multi-Processor Interrupt Controller (MPIC)
  109
  - MPIC Features
    109
  - Architecture
    110
  - External Interrupt Interface
    110
  - Csr's Readability
    111
  - Interrupt Source Priority
    111
  - Figure 2-9 Serial Mode Interrupt Scan
    111
  - Processor's Current Task Priority
    112
  - Nesting of Interrupt Events
    112
  - Spurious Vector Generation
    112
  - Interprocessor Interrupts (IPI)
    112
  - 8259 Compatibility
    113
  - Hawk Internal Error Interrupt
    113
  - Timers
    113
  - Interrupt Delivery Modes
    114
  - Block Diagram Description
    114
  - Figure 2-10 MPIC Block Diagram
    116
  - Programming Notes
    119
  - Operation
    121
  - Architectural Notes
    123
  - Effects of Interrupt Serialization
    123
- Registers
  124
  - PPC Registers
    124
  - Table 2-23 Revision ID Register
    124
  - Table 2-20 PPC Register Map for PHB
    125
  - Table 2-44 PCI Interrupt Acknowledge Register
    125
  - Table 2-21 Vendor ID/Device ID Registers
    126
  - Revision ID Register
    127
  - Time-Out Length
    129
  - Ppc ID
    129
  - PPC Arbiter/Pci Arbiter Control Registers
    130
  - Flatten Single Write Field
    130
  - Parking Field
    131
  - Priority Field
    132
  - Parking Field
    132
  - Table
    133
  - Hierarchy Field
    133
  - Hierarchy Field - Mixed Priority Scheme
    133
  - Table 2-33 Hardware Control-Status/Prescaler Adjust Register
    134
  - PPC/PCI Clock Ratio Field
    135
  - Write Lock Resolution Threshold
    135
  - Read Lock Resolution Threshold
    136
  - Table 2-37 Common Scale Factors for Common CLK Frequencies
    136
  - PPC Error Test/Error Enable Register
    137
  - Table 2-39 PPC Error Status Register
    140
  - PPC Error Address Register
    141
  - PPC Error Attribute Register
    142
  - PPC Error Attribute Register, PSMA or PRTA Set
    143
  - PCI Interrupt Acknowledge Register
    144
  - PPC Slave Offset/Attribute (0, 1 and 2) Registers
    145
  - PPC Slave Address (3) Register
    146
  - PPC Slave Offset/Attribute (3) Registers
    147
  - Wdtxcntl Registers
    148
  - RES Field Options
    149
  - Wdtxstat Registers
    151
  - PCI Registers
    152
  - Table 2-48 Table
    152
  - General Purpose Registers
    152
  - PCI Configuration Register
    152
  - Table
    153
  - PCI I/O Register
    153
  - Vendor ID/ Device ID Registers
    154
  - PCI Command/ Status Registers
    154
  - Revision ID/ Class Code Registers
    156
  - Header Type Register
    157
  - MPIC I/O Base Address Register
    158
  - MPIC Memory Base Address Register
    158
  - PCI Slave Address (0,1,2, and 3) Registers
    160
  - PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
    161
  - Rmftx Field
    162
  - Wxftx Field
    162
  - Table 2-64 Conceptual Perspective from the PCI Bus
    163
  - Table 2-65 Perspective from the PPC Bus in Big Endian Mode
    163
  - Table 2-66 Perspective from the PPC Bus in Little Endian Mode
    164
  - Table 2-67 Conceptual Perspective from the PCI Bus
    165
  - Table 2-68 Perspective from the PPC Bus in Big Endian Mode
    165
  - MPIC Registers
    166
  - Table 2-69 Perspective from the PPC Bus in Little Endian Mode
    166
  - MPIC Register Map
    167
  - Feature Reporting Register
    169
  - Global Configuration Register
    170
  - Cascade Mode Encoding
    171
  - Tie Mode Encoding
    171
  - Vendor Identification Register
    172
  - Processor Init Register
    172
  - IPI Vector/Priority Registers
    173
  - Spurious Vector Register
    174
  - Timer Frequency Register
    174
  - Timer Current Count Registers
    175
  - Timer Basecount Registers
    176
  - Timer Vector/Priority Registers
    177
  - Timer Destination Registers
    178
  - External Source Vector/Priority Registers
    178
  - External Source Destination Registers
    180
  - Table 2-86 Hawk Internal Error Interrupt Vector/Priority Register
    180
  - Hawk Internal Error Interrupt Destination Register
    182
  - Interprocessor Interrupt Dispatch Registers
    182
  - Current Task Priority Registers
    183
  - Interrupt Acknowledge Registers
    184
  - End-Of-Interrupt Registers
    184
3 System Memory Controller (SMC)

187
- Overview
  187
- Functional Description
  192
  - Figure 3-4 Hawk's System Memory Controller Block Diagram
    192
  - SDRAM Accesses
    193
  - Ppc60X Bus Interface
    196
  - SDRAM Organization
    196
  - Sdram Ecc
    198
  - Error Reporting
    199
  - Error Logging
    200
  - Rom/Flash Interface
    201
  - Ppc60X to Rom/Flash (16 Bit Width) Address Mapping
    202
  - Ppc60X to Rom/Flash (64 Bit Width) Address Mapping
    204
  - Ppc60X Bus to Rom/Flash Access Timing (120Ns @ 100 Mhz)
    206
  - Table
    206
  - Table 2-52 Table
    206
  - Ppc60X Bus to Rom/Flash Access Timing (50Ns @ 100 Mhz)
    207
  - Ppc60X Bus to Rom/Flash Access Timing (80Ns @ 100 Mhz)
    207
  - I2C Interface
    208
  - Ppc60X Bus to Rom/Flash Access Timing (30Ns @ 100 Mhz)
    208
  - Figure 3-5 Programming Sequence for I2C Byte Write
    212
  - Figure 3-6 Programming Sequence for I2C Random Read
    215
  - Figure 3-7 Programming Sequence for I2C Current Address Read
    218
  - Figure 3-8 Programming Sequence for I2C
    221
  - Figure 3-9 Programming Sequence for I2C Sequential Read
    225
  - Chip Configuration
    226
  - CSR Accesses
    226
  - External Register Set
    226
  - Refresh/Scrub
    226
- Programming Model
  227
  - CSR Architecture
    227
  - Register Summary
    228
  - Detailed Register Bit Descriptions
    230
  - Table 3-10 Possible Operations for each Bit in the Register
    230
  - Table 3-11 Possible States of the Bits
    230
  - Vendor/Device Register
    232
  - Revision ID/General Control Register
    232
  - SDRAM Enable and Size Register (Blocks A, B, C, D)
    234
  - Table 3-15 Block_A/B/C/D/E/F/G/H Configurations
    235
  - SDRAM Base Address Register (Blocks A/B/C/D)
    236
  - CLK Frequency Register
    237
  - Table 3-18 DRR and CLK Frequency Examples
    238
  - ECC Control Register
    239
  - Figure 3-10 Read/Write Check-Bit Data Paths
    240
  - Error Logger Register
    243
  - Error_Address Register
    244
  - Scrub/Refresh Register
    245
  - Scrub Address Register
    246
  - ROM a Base/Size Register
    247
  - Table 3-25 ROM Block a Size Encoding
    248
  - Table 3-26 Rom_A_Rv and Rom_B_Rv Encoding
    248
  - Table 3-27 Read/Write to Rom/Flash
    249
  - ROM B Base/Size Register
    250
  - Table
    251
  - ROM Block B Size Encoding
    251
  - ROM Speed Attributes Registers
    252
  - Table 3-31 ROM Speed Bit Encoding
    252
  - Data Parity Error Log Register
    253
  - Data Parity Error Address Register
    254
  - Data Parity Error Upper Data Register
    255
  - Data Parity Error Lower Data Register
    255
  - I2C Clock Prescaler Register
    256
  - I2C Control Register
    256
  - I2C Status Register
    257
  - I2C Transmitter Data Register
    258
  - I2C Receiver Data Register
    259
  - SDRAM Enable and Size Register (Blocks E,F,G,H)
    260
  - SDRAM Base Address Register (Blocks E/F/G/H)
    261
  - SDRAM Speed Attributes Register
    262
  - Trc Encoding
    263
  - Tras Encoding
    264
  - Address Parity Error Log Register
    265
  - Address Parity Error Address Register
    266
  - 32-Bit Counter
    266
  - External Register Set
    267
  - Tben Register
    268
- Software Considerations
  269
- ECC Codes
  280
- MPIC Interrupt Assignments
  283
  - Pci Arbitration
    283
  - Interrupts
    285
  - Table 4-2 PBC ISA Interrupt Assignments
    285
- Exceptions
  286
  - Error Notification and Handling
    287
  - Soft Reset
    287
- Endian Issues
  288

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