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ATCA-7370
Artesyn Embedded Technology ATCA-7370 Manuals
Manuals and User Guides for Artesyn Embedded Technology ATCA-7370. We have
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Artesyn Embedded Technology ATCA-7370 manuals available for free PDF download: Installation And Use Manual, Quick Start Manual
Artesyn Embedded Technology ATCA-7370 Installation And Use Manual (252 pages)
Brand:
Artesyn Embedded Technology
| Category:
Motherboard
| Size: 15 MB
Table of Contents
Table of Contents
3
About this Manual
19
Figure
24
Safety Notes
25
Sicherheitshinweise
31
1 Introduction
37
Features
37
Standard Compliances
38
Table 1-1 Standard Compliances
38
Figure 1-1 Declaration of Conformity
40
Mechanical Data
41
Mechanical Layout
42
Figure 1-2 Mechanical Layout
42
Mean Time between Failures
43
Ordering Information
43
Table 1-3 Blade Variants - Ordering Information
43
Table 1-4 Blade Accessories - Ordering Information
43
Product Identification
44
2 Hardware Preparation and Installation
45
Unpacking and Inspecting the Blade
45
Environmental and Power Requirements
45
Environmental Requirements
46
Table 2-1 Environmental Requirements
46
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)
48
Power Requirements
49
Table 2-2 Power Requirements
49
Blade Layout
51
Installing the Blade Accessories
52
DIMM Memory Modules
52
Cave Creek Module
54
Figure 2-3 Cave Creek Module
54
Figure 2-4 Cave Creek Module Installation
56
Installing and Removing the Blade
57
Installing the Blade
57
Removing the Blade
59
3 Controls, Indicators, and Connectors
61
Faceplate
61
Leds and Interfaces
61
Faceplate Leds
62
Connectors
64
Faceplate Connectors
64
Table 3-2 RJ45 Console Connector Pinout
64
Backplane Connectors
65
Table 3-3 USB Connector Pinout
65
Table 3-4 Zone 1 Connector P1 Pin Assignment
65
Table 3-5 Zone 2 Connector J20 Pin Assignment
66
Table 3-6 Zone 2 Connector J23 Pin Assignment
66
Table 3-7-7 Zone 3-7 Connector J3-70 Pin Assignment
67
Table 3-8 Zone 3 Connector J31 Pin Assignment
67
Table 3-9 Zone 3 Connector J32 Pin Assignment
68
Mezzanine Card Connector
69
Table 3-10 Mezzanine Card Connector Signals
69
Onboard Connectors
71
TPM Head
71
Figure 3-2 TPM Connector Pinout
71
FPGA JTAG Head
72
Switch Settings
72
PCH Switch
72
Figure 3-3 USB 2.0 Flash Disk Module Connector Pinout
72
FPGA Switch
73
Table 3-12 Switch SW1 Setting
73
4 Bios
75
Features
75
Update and Recovery
76
DRAM Support
77
Interrupt Routing
79
PCI Initialization
79
I/O Device Configuration
79
Serial Ports
79
Integrated SATA Controller
79
Boot Options
80
Boot Support for the SAS Controller
80
Network Boot
81
Table 4-1 Network Boot Support Status
81
I/O Redirection
82
Console Redirection
82
Serial over LAN (SOL)
82
IPMI Support
82
Watchdogs
83
SMBIOS Support
83
LED Behavior During POST
84
BIOS Setup Layout
84
Board Information Display
84
USB 2.0 Ports
84
Supported Operating Systems
84
SPI Boot Flash
85
Serial Console and BIOS Printouts
85
BIOS Printouts to DRAM
85
Table 4-2 Printout Floating Structure
85
BIOS Interface Towards os
86
Proprietary BIOS Data Area (BDA) Bytes
86
BIOS CLI Tool - IPMIBPAR
86
Setup Utility
87
Table 4-4 Primary Menu Description
87
Main Menu
89
Table 4-6 Main Menu Description
89
Advanced Menu
90
Table 4-7 Advanced Menu Description
90
Boot Configuration
91
Table 4-8 Boot Configuration Description
91
Processor Configuration
93
Table 4-9 Processor Configuration Description
93
HDD Configuration
94
Peripheral Configuration
94
Table 4-10 Peripheral Configuration Description
94
Table 4-11 HDD Configuration Description
94
Memory Configuration
95
Table 4-12 Memory Configuration Description
95
South Bridge Configuration
96
Table 4-13 South Bridge Configuration Description
96
Table 4-14 SB USB Configuration Description
96
SMBIOS Event Log
97
Table 4-15 SMBIOS Event Log Description
97
Security Menu
98
Table 4-16 Security Menu Description
98
Boot Menu
99
Table 4-17 Boot Menu Description
99
Save and Exit Menu
100
Table 4-18 Save and Exit Menu Description
100
5 Functional Description
103
Block Diagram
103
Processor
104
Figure 5-2 Intel Xeon Processor E5-2648L/C604 Chipset Platform Overview
104
Memory
105
DDR3 Main Memory
105
Network
105
I/O Controller
105
Figure 5-3 PCH Block Diagram
106
Ethernet Ports
107
ATCA 3.0 Base Interface
107
Fabric Interface ATCA 3.1
107
Faceplate Ethernet Ports
107
Update Channel Ethernet
108
Storage
108
Ipmc
108
Serial Redirection
109
Real Time Clock
109
Serial ATA
109
IPMI over LAN
110
USB 2.0 Interface
110
Smbus Connections
111
Figure 5-4 Overall Smbus Connections
111
Glue Logic FPGA
112
6 Maps and Registers
113
Interrupt Structure
113
Figure 6-1 Interrupt Structure on ATCA-7370
113
Table 6-1 Interrupt Source Signals List
114
PIC (Non-APIC) D31:F0 Interrupt Mapping
115
Table 6-2 Non-APIC (PIC Mode/8259 Mode) Interrupt Mapping
115
APIC (D31:F0) Interrupt Mapping
116
Table 6-3 APIC Mode Interrupt Mapping
116
Non-Maskable Interrupt Generation
118
Registers
120
Table 6-5 Causes of Interrupt
120
Table 6-7 Register Access Type
120
Register Decoding
121
LPC Decoding
122
Table 6-8 LPC I/O Register Map Overview
122
SPI Register Decoding
123
POST Code Register
123
Table 6-10 POST Code Register
123
Super IO Configuration Register
124
Entering the Configuration State
124
Exiting the Configuration State
124
Table 6-11 Super I/O Configuration Index Register
124
Table 6-12 Super I/O Configuration Data Register
124
Configuration Mode
125
Super I/O Configuration Registers
125
Table 6-13 Global Configuration Register Summary
125
Table 6-14 Super IO Logical Device Number Register
126
Table 6-15 Super IO Device Revision Register
126
Table 6-16 Super IO LPC Control Register
126
Table 6-17 Global Super IO SERIRQ and Pre-Divide Control Register
127
Table 6-18 Logical Device Configuration Register Summary
127
Table 6-19 Logical Device Enable Register
128
Table 6-20 Logical Device Base IO Address MSB Register
128
Table 6-21 Logical Device Base IO Address LSB Register
128
Table 6-22 Logical Device Common Decode Ranges
129
Table 6-23 Logical Device Primary Interrupt Register
129
Table 6-24 Logical Device 0X74 Reserved Register
130
Table 6-25 Logical Device 0X75 Reserved Register
130
Table 6-26 Logical Device 0Xf0 Reserved Register
130
UART1 and UART2 Register Map
131
UART Register Overview
131
Table 6-27 UART Register Overview
131
UART Registers DLAB=0
132
Receiver Buffer Register
132
Transmitter Holding Register (THR)
132
Table 6-28 Receiver Buffer Register (RBR) if DLAB=0
132
Table 6-29 Transmitter Holding Register (THR) if DLAB=0
132
Interrupt Enable Register (IER)
133
Table 6-30 Interrupt Enable Register (IER), if DLAB=0
133
Interrupt Identification Register (IIIR)
134
Table 6-31 UART Interrupt Priorities2
134
Table 6-32 Interrupt Identification Register (IIIR)
134
Table 6-33 Interrupt Identification Register Decode
135
FIFO Control Register (FCR)
136
Table 6-34 FIFO Control Register (FCR)
136
Line Control Register (LCR)
137
Table 6-35 Line Control Register (LCR)
137
Modem Control Register (MCR)
139
Table 6-36 Modem Control Register (MCR)
139
Line Status Register (LSR)
140
Table 6-37 Line Status Register (LSR)
141
Modem Status Register (MSR)
144
Table 6-38 Modem Status Register (MSR)
145
Scratch Register (SCR)
147
Programmable Baud Rate Generator
147
Table 6-39 Scratch Register (SCR)
147
FPGA Register Mapping
148
LPC I/O Register Map
148
Table 6-40 Divisor Latch LSB Register (DLL), if DLAB=1
148
Table 6-41 Divisor Latch MSB Register (DLM), if DLAB=1
148
IPMC SPI Register Map
149
Table 6-42 FPGA Register Map Overview
149
Module Identification Register
151
Table 6-43 Module Identification Register
151
Version Register
152
Serial Redirection Console Register
152
Table 6-45 Serial Redirection Control Register
152
Serial over LAN (SOL) Control Register
153
Serial Routing Register
153
Table 6-46 SOL Control Register
153
Table 6-47 Serial Routing Register
153
IPMC Power Level Register
154
Table 6-48 IPMC Power Level Register
154
Payload Power Control Register
155
I2C Switch Control Register
155
Table 6-49 Payload Power Control Register
155
Table 6-50 I2C Switch Control Register
155
Payload Power-Button Register
156
Reset Registers
156
Reset Mask Register
156
Table 6-51 Payload Power-Button Register
156
Reset Function Register
157
Table 6-53 Reset Function Register
157
IPMC Reset Payload Request Register
158
Table 6-54 IPMC Reset Payload Request Register
158
BIOS Reset Payload Request Register
159
OS Reset Payload Request Register
159
Table 6-55 BIOS Reset Payload Request Register
159
Table 6-56 os Reset Payload Request Register
159
Payload Reset Source for IPMC Register
160
Payload Reset Source for BIOS Register
160
Table 6-57 Payload Reset Source for IPMC Register
160
Payload Reset Source for os Register
161
Table 6-58 Payload Reset Source for BIOS Register
161
Table 6-59 Payload Reset Source for os Register
162
IPMC Watchdog Timeout Register
163
10IPMC Watchdog Timeout for BIOS Register
163
Table 6-60 IPMC Watchdog Timeout Register
163
Table 6-61 IPMC Watchdog Timeout for BIOS Register
163
11IPMC Watchdog Timeout for os Register
164
12FPGA-Payload-Watchdog Threshold Register
164
Table 6-62 IPMC Watchdog Timeout for os Register
164
Table 6-63 FPGA-Payload-Watchdog Threshold Low-Byte Register
164
13FPGA Payload Watchdog Clear Register
165
14FPGA-IPMC-Watchdog Threshold Register
165
Table 6-64 FPGA-Payload-Watchdog Clear Register
165
Table 6-65 FPGA-IPMC-Watchdog Threshold Register
165
Flash Control Register
166
RTM Status and Control Register
166
Table 6-66 Flash Control Register
166
Table 6-67 RTM Status and Control Register
166
Blue LED Status and Control Register
167
Table 6-68 User LED Status and Control Register
167
User LED Status and Control Register
168
Table 6-69 User LED Status and Control Register
168
Miscellaneous Status and Control Register
169
Debug Switch and LED Status Register
169
Table 6-70 Miscellaneous Status and Control Register
169
Table 6-71 Debug Switch and LED Status Register
169
Scratch Register
170
POST Code Register
170
Standard Status Codes
170
Table 6-72 LPC Scratch Registers
170
Table 6-73 POST Code Register
170
Table 6-74 Component Status Codes
170
Table 6-75 Progress Status Codes
173
Table 6-76 Architectural Status Codes
174
7 Serial over LAN
175
Overview
175
Installing the Ipmitool
175
SOL Overview
175
Configuring SOL Parameters
176
Using Standard IPMI Commands
176
Using Ipmitool
177
Establishing a SOL Session
179
8 Supported IPMI Commands
181
Standard IPMI Commands
181
Global IPMI Commands
181
System Interface Commands
181
Table 8-1 Supported Global IPMI Commands
181
Table 8-2 Supported System Interface Commands
181
BMC Watchdog Commands
182
Table 8-3 Supported Watchdog Commands
182
SEL Device Commands
183
FRU Inventory Commands
183
Table 8-4 Supported SEL Device Commands
183
Table 8-5 Supported FRU Inventory Commands
183
Sensor Device Commands
184
Chassis Device Commands
184
Table 8-6 Supported Sensor Device Commands
184
Table 8-7 Supported Chassis Device Commands
184
System Boot Options Commands
185
Table 8-8 Configurable System Boot Option Parameters
185
Table 8-9 System Boot Options Parameter #96
186
Table 8-10 System Boot Options Parameter #97
187
Table 8-11 System Boot Options Parameter #98
188
Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview
189
Table 8-12 System Boot Options - Parameter #100 - Data Format
190
Table 8-13 System Boot Options Parameter #100 - SET Command Usage
190
Table 8-14 System Boot Options Parameter #100 - GET Command Usage
191
Table 8-15 System Boot Options Parameter #100 - Supported Parameters
194
Table 8-16 Boot_Order Devices
194
Event Commands
195
LAN Device Commands
195
Table 8-17 Supported Event Commands
195
Table 8-18 Supported LAN Device Commands
195
PICMG 3.0 Commands
196
Table 8-19 Supported PICMG 3.0 Commands
196
Artesyn Embedded Technologies Specific Commands
198
Set/Get Feature Configuration Commands
198
Table 8-20 Set/Get Feature Configuration Commands
198
Get Feature Configuration Command
199
Set Feature Configuration Command
199
Table 8-21 Set Feature Configuration Command
199
Table 8-22 Get Feature Configuration Command
199
Serial Output Commands
200
Table 8-23 Feature Selector Assignments
200
Table 8-24 Serial Output Commands
200
Get Serial Output Command
201
Set Serial Output Command
201
Table 8-25 Set Serial Output Command
201
OEM Set/Get ACPI Power Commands
202
Table 8-26 Get Serial Output Command
202
Table 8-27 OME Set/Get ACPI Power Commands
202
OEM Get ACPI Power State (0X18)
203
OEM Set ACPI Power State (0X17)
203
Table 8-28 OEM Set ACPI Power State Command
203
OEM Set/Get Performance Commands
204
Table 8-29 OEM Get ACPI Power State Command
204
Table 8-30 OEM Set/Get Performance Commands
204
OEM Set Performance Mode (0X21)
205
Table 8-31 OEM Set Performance Mode Command
205
OEM Get Performance Mode (0X22)
206
Table 8-32 OEM Get Performance Mode Command
206
Pigeon Point Specific Commands
207
Table 8-33 Pigeon Point Extension Commands
207
Get Status Command
208
Table 8-35 Get Status Command Description
208
Get Serial Interface Properties Command
211
Table 8-36 Get Serial Interface Properties Command Description
211
Set Serial Interface Properties Command
212
Table 8-37 Set Serial Interface Properties Command Description
212
Get Debug Level Command
213
Table 8-38 Get Debug Level Command Description
213
Set Debug Level Command
214
Table 8-39 Set Debug Level Command Description
214
Get Hardware Address Command
215
Set Hardware Address Command
215
Table 8-40 Get Hardware Address Command Description
215
Table 8-41 Set Hardware Address Command Description
215
Get Handle Switch Command
216
Table 8-42 Get Handle Switch Command Description
216
Get Payload Communication Time-Out Command
217
Set Handle Switch Command
217
Table 8-43 Set Handle Switch Command Description
217
Table 8-44 Get Payload Communication Time-Out Command Description
217
Set Payload Communication Time-Out Command
218
Table 8-45 Set Payload Communication Time-Out Command Description
218
Disable Payload Control Command
219
Enable Payload Control Command
219
Table 8-46 Enable Payload Control Command Description
219
Table 8-47 Disable Payload Control Command Description
219
Hang IPMC Command
220
Reset IPMC Command
220
Table 8-48 Reset IPMC Command Description
220
Table 8-49 Hang IPMC Command Description
220
Graceful Reset Command
221
Table 8-50 Graceful Reset Command Description
221
Get Payload Shutdown Time-Out Command
222
Table 8-51 Get Payload Shutdown Time-Out Command Description
222
Get Module State Command
223
Set Payload Shutdown Time-Out Command
223
Table 8-52 Set Payload Shutdown Time-Out Command Description
223
Table 8-53 Get Module State Command Description
223
Disable Module Site Command
225
Enable Module Site Command
225
Table 8-54 Enable Module Site Command Description
225
Table 8-55 Disable Module Site Command Description
225
Reset Carrier SDR Repository Command
226
Table 8-56 Reset Carrier SDR Repository Command Description
226
9 FRU Information and Sensor Data Records
227
FRU Information
227
Power Configuration
228
Table 9-2 Power Configuration
228
Sensor Data Records
229
Block Diagram
229
Table 9-3 Sensor Data Records
230
10 Firmware Upgrade
241
HPM.1 Firmware Upgrade
241
Overview
241
Installing the Ipmitool
241
Update Procedure
241
Interface
241
KCS Interface
242
Ipmb-0
242
IPMI over LAN (BASE)
242
IPMC Upgrade
243
Figure 10-1 IPMC Component Elements
243
BIOS/FPGA Update
244
Figure 10-2 SPI Busses Connection
244
Upgrade Package
245
Table 10-1 HPM Upgrade Package
245
Troubleshooting
247
Error List
247
CPU Blade Is Not Functioning Properly
247
Related Documentation
249
Artesyn Embedded Technologies - Embedded Computing Documentation
249
Related Specifications
249
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications
249
Table B-2 Related Specifications
249
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Artesyn Embedded Technology ATCA-7370 Quick Start Manual (2 pages)
Brand:
Artesyn Embedded Technology
| Category:
Motherboard
| Size: 0 MB
Table of Contents
What’s in the Box?
1
Install the DIMM
1
Prepare the Installation Site
1
Install the Blade
2
Install the Cave Creek Module
2
Install the Blade (Cont.)
2
Finding more Information
2
Technical Assistance
2
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