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Artesyn Embedded Technology ATCA-7365-CE manual available for free PDF download: Installation And Use Manual
Artesyn Embedded Technology ATCA-7365-CE Installation And Use Manual (288 pages)
Brand:
Artesyn Embedded Technology
| Category:
Server
| Size: 3 MB
Table of Contents
Table of Contents
3
About this Manual
19
Table
25
Table 6-7 Table
25
Safety Notes
27
Sicherheitshinweise
31
1 Introduction
37
Features
37
Standard Compliances
38
Table 1-1 Standard Compliances
38
Mechanical Data
39
Product Identification
40
Figure 1-1 Serial Number Location
40
Ordering Information
41
Blade Variants
41
2 Hardware Preparation and Installation
43
Unpacking and Inspecting the Blade
43
Environmental and Power Requirements
44
Environmental Requirements
44
Table 2-2 Critical Temperature Limits
45
Table 2-1 Environmental Requirements
45
Figure 2-1 Location of Critical Temperature Spots
46
Power Requirements
47
Table 2-3 Power Requirements
47
Blade Layout
49
Figure 2-2 ATCA-7365-CE Blade Layout
49
Switch Settings
50
Table 2-4 Switch Settings
51
Installing the Blade Accessories
52
DIMM Memory Modules
53
PMEM and SATA Module
55
USB 2.0 Flash Module
56
Installing and Removing the Blade
57
Installing the Blade
58
Removing the Blade
61
3 Controls, Indicators, and Connectors
63
Mechanical Layout
63
Figure 3-1 Mechanical Layout
63
Faceplate
64
Figure 3-3 Faceplate (with VGA Module)
65
Figure 3-4 Location of Faceplate Leds
66
Leds
66
Table 3-1 Faceplate Leds
67
Figure 3-5 Location of Faceplate Reset Key
68
Keys
68
Connectors
69
Ethernet Connector
69
Figure 3-6 Location of Ethernet Connector
69
Figure 3-7 Ethernet Interface Connectors Pinout
69
Serial Interface Connector
70
Figure 3-8 Location of Serial Connector
70
Figure 3-9 Serial Interface Connector Pinout
70
USB Connectors
71
Figure 3-10 Location of USB Connectors
71
Figure 3-11 USB Connector Pinout
71
VGA-7360 Module Connector
72
Table 3-2 VGA-7360 Module Connector Pinout
72
Table 3-3 Faceplate VGA Connector Signals
72
On-Board Connectors
73
PMEM/SFMEM Module Connector
73
Figure 3-12 Location Ofpmem/Sfmem Module Connector
74
Figure 3-13 PMEM/SATA Module Connector Pinout
75
USB Flash Module Connector
76
Figure 3-14 Location of USB Flash Module Connector
76
Figure 3-15 USB Flash Module Connector Pin Assignment
77
Advancedtca Backplane Connectors
78
Figure 3-16 Location of Advancedtca Connectors
78
Figure 3-17 P10 Backplane Connector Pinout
79
Figure 3-18 P20 Backplane Connector Pinout - Rows a to D
80
Figure 3-19 P20 Backplane Connector Pinout - Rows E to H
81
Figure 3-20 P23 Backplane Connector Pinout - Rows a to D
81
Figure 3-21 P23 Backplane Connector Pinout - Rows E to H
82
Figure 3-22 P30 Backplane Connector Pinout - Rows a to D
83
Figure 3-23 P30 Backplane Connector Pinout - Rows E to H
83
Figure 3-24 P32 Backplane Connector Pinout - Rows a to D
84
Figure 3-25 P32 Backplane Connector Pinout - Rows E to H
84
4 Bios
85
Introduction
85
Accessing the Blade Using the Serial Console Redirection
86
Requirements for Serial Console Redirection
86
Table 4-1 BIOS Key Codes for Terminal Emulation Program
86
Default Access Parameters
87
Connecting to the Blade
87
Changing Configuration Settings
87
Boot Options
89
Supported Boot Devices
89
Selecting the Boot Device
89
By Boot Selection Menu
91
Iscsi Setup for Base and Fabric Ethernet
92
Figure 4-4 Option ROM Execution
92
Figure 4-5 Iscsi Boot Configuration
93
Iscsi Boot Configuration
93
Figure 4-6 Iscsi Port Configuration
94
Iscsi Port Configuration
94
Figure 4-7 Iscsi Port Selection
95
ISCSI Port Selection
95
Table 4-2 Ethernet Port Mapping
95
Table 4-3 Select Iscsi Boot Priority Hot Keys
96
Iscsi Challenge Handshake Authentication Protocol (CHAP) Configuration
97
BIOS Setup Configuration
97
Main
97
Figure 4-8 Iscsi CHAP Configuration
97
Advanced Menu
98
Advanced -> CPU Configuration
98
Table 4-5 CPU Configuration
98
Advanced -> Memory Configuration
100
Table 4-6 Memory Configuration
100
Advanced -> Chipset - North Bridge
101
Table 4-7 Chipset - North Bridge
101
Table 4-8 Chipset - North Bridge -> Intel(R) VT for Directed I/O Configuration
102
Advanced -> Chipset - South Bridge
103
Table 4-9 Chipset - North Bridge -> IOH Thermal Sensors
103
Table 4-10 Chipset - South Bridge
103
Table 4-11 Chipset - South Bridge -> USB Configuration
103
Table 4-24 Table
103
Advanced -> SATA Configuration
104
Table 4-12 Advanced -> SATA Configuration
104
Advanced -> USB Configuration
105
Table 4-13 Advanced -> USB Configuration
105
Advanced -> Super IO Configuration
106
Advanced -> Serial Port Console Redirection
106
Table 4-14 Super IO Configuration -> Serial Port 0 Configuration
106
Table 4-15 Advanced -> Serial Port Console Redirection
106
Table 4-16 Serial Port Console Redirection -> Console Redirection Settings
107
Advanced -> UEFI Network Stack
108
Advanced -> Runtime Error Logging
108
Advanced -> SMBIOS Event Log
108
Table 4-17 Advanced -> UEFI Network Stack
108
Table 4-18 Advanced -> Runtime Error Logging
108
Advanced -> Local IPMI System Event Log
109
Table 4-19 SMBIOS Event Log -> SMBIOS Event Log Settings
109
Table 4-20 Advanced -> Local IPMI System Event Log
109
Advanced -> WHEA Configuration
110
Ipmi
110
IPMI -> IPMI Watchdog Configuration
110
Table 4-21 Advanced -> WHEA Configuration
110
Table 4-22 IPMI -> IPMI Watchdog Configuration
110
IPMI -> System Event Log
111
Iscsi
111
Table 4-23 IPMI -> System Event Log
111
Boot
112
Boot -> Option ROM Execution
113
Table 4-26 Boot -> Option ROM Execution
113
Security
114
Save & Exit
114
CPU Performance Settings
114
Memory Configuration
115
Independent Channel Mode
115
Spare Channel Mode
116
Mirrored Channel Mode
116
Lockstep Channel Mode
116
Restoring BIOS Default Settings
117
Shelf Slot Power Requirement
117
LED Usage
118
Upgrading the BIOS
118
BIOS Error Logging
118
Runtime Error Logging
119
Table 4-28 Logged Error Events
119
Error Simulation
120
IPMI Error Logging
121
Table 4-29 BIOS Supported IPMI Events
121
SMBIOS Error Logging
123
Single-Bit ECC Memory Error
124
Multi-Bit ECC Memory Error
124
Table 4-30 Single-Bit ECC Memory Error Event Format
124
Table 4-31 Memory Information Definition
124
Table 4-32 Multi-Bit ECC Memory Error Event Format
124
POST Error
125
Table 4-33 Memory Information Definition
125
Table 4-34 POST Error Event Format
125
Table 4-35 Result First DWORD Supported POST Errors
126
Table 4-36 Result Second DWORD Supported POST Errors
126
PCI Parity Error
127
PCI System Error
127
Table 4-37 PCI Parity Error Event Format
127
Table 4-38 PCI Information Definition
127
Table 4-39 Multi-Bit ECC Memory Error Event Format
127
CPU Failure
128
Correctable Memory Log Disabled
128
Table 4-40 Memory Information Definition
128
Table 4-41 CPU Failure Event Format
128
Log Area Reset/Cleared
129
Table 4-42 Correctable Memory Log Disabled Event Format
129
Table 4-43 Memory Information Definition
129
Table 4-44 Log Area Reset/Cleared Event Format
129
System Boot
130
10OEM Event EFI Status Code
130
Table 4-45 System Boot Event Format
130
Table 4-46 System Boot Event Format
130
Table 4-47 Status Code Type Definition
131
Table 4-48 Status Code Value Definition
131
Table 4-50 Subclass EFI_COMPUTING_UNIT_CHIPSET (06H)
131
BIOS Status Codes
132
Table 4-51 Subclass EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (02H) (IPMI)
132
Standard Status Codes
133
Table 4-52 Status Code Ranges
133
Table 4-54 PEI Status Codes
134
Table 4-55 DXE Status Codes
136
Status Code Ranges
133
5 Functional Description
141
Block Diagram
141
Processor
142
Memory
142
Persistent Memory (PMEM Module)
143
Chipset
143
I/O Controller
143
Firmware Flashes
144
Ethernet Ports
144
Storage Controller
145
Embedded Flash Disk
145
SATA Embedded Flash Solid State Disc (SSD)
145
Table 5-1 Ethernet Controller Types
145
Bios
146
Ipmc
146
Serial Redirection
147
Serial over LAN
147
Control Logic
148
Front Board Faceplate
148
USB 2.0 Interface
148
Smbus Interface
149
Real Time Clock
150
VGA Module
150
Graphics Engine
151
Figure 5-2 VGA-7360 Module (Front and Back View)
151
Supported VGA Graphics Modes
152
6 Maps and Registers
153
Interrupt Structure
153
Figure 6-1 Interrupt Structure on ATCA-7365
153
Table 6-1 APIC Mode Interrupt Mapping
154
Table 6-2 Non-APIC (PIC Mode/8259 Mode) Interrupt Mapping
155
PCI Express Port Mapping
156
Table 6-3 PCI Express Port Mapping
156
Figure 6-2 IOH36D Pcie Port Mapping on ATCA-7365
156
Registers
157
Table 6-5 Register Access Type
157
Register Decoding
158
LPC Decoding
158
Table 6-6 LPC I/O Register Map Overview
158
SPI Register Decoding
159
POST Code Register
159
Super IO Configuration Register
160
Entering the Configuration State
160
Configuration Mode
160
Table 6-9 Super IO Configuration Index Register
160
Table 6-10 Super IO Configuration Data Register
160
Super IO Configuration Registers
161
Table 6-11 Global Configuration Register Summary
161
Table 6-12 Super IO Logical Device Number Register
162
Table 6-13 Super IO Device Identification Register
162
Table 6-14 Super IO Device Revision Register
162
Table 6-15 Super IO LPC Control Register
162
Table 6-16 Global Super IO SERIRQ and Pre-Divide Control Register
163
Table 6-17 Logical Device Configuration Register Summary
163
Table 6-18 Logical Device Enable Register
164
Table 6-19 Logical Device Base IO Address MSB Register
164
Table 6-20 Logical Device Base IO Address LSB Register
164
Table 6-21 Logical Device Common Decode Ranges
165
Table 6-22 Logical Device Primary Interrupt Register
165
UART1 and UART2 Register Map
166
UART Register Overview
166
Table 6-23 Logical Device 0X74 Reserved Register
166
Table 6-24 Logical Device 0X75 Reserved Register
166
Table 6-25 Logical Device 0Xf0 Reserved Register
166
Table 6-26 UART Register Overview
167
Table 6-35 Line Control Register (LCR)
167
UART Registers DLAB=0
168
Table 6-27 Receiver Buffer Register (RBR) if DLAB=0
168
Table 6-28 Transmitter Holding Register (THR) if DLAB=0
168
Table 6-29 Interrupt Enable Register (IER), if DLAB=0
169
Table 6-30 UART Interrupt Priorities
170
Table 6-31 Interrupt Identification Register (IIR)
170
Table 6-32 FIFO Control Register (FCR)
171
Table 6-33 Line Control Register (LCR)
172
Table 6-34 Modem Control Register (MCR)
174
Table 6-36 Modem Status Register (MSR)
179
Programmable Baud Rate Generator
180
Table 6-37 Scratch Register (SCR))
180
FPGA Register Mapping
181
LPC I/O Register Map
181
Table 6-38 Divisor Latch LSB Register (DLL), if DLAB=1
181
Table 6-39 Divisor Latch MSB Register (DLM), if DLAB=1
181
IPMC SPI Register Map
182
Table 6-40 FPGA Register Map Overview
182
Module Identification Register
183
Table 6-41 Module Identification Register
183
Version Register
184
Serial Redirection Control Register
184
Table 6-43 Serial Redirection Control Register
184
Serial over LAN (SOL) Control Register
185
Table 6-44 Serial over LAN Control Register
185
Serial Line Routing Register
186
IPMC Power Level Register
186
Table 6-45 Serial Line Routing Register
186
Table 6-46 IPMC Power Level Register
186
SPD PROM MUX Control Register
187
Table 6-47 SPD PROM MUX Control Register
187
Reset Registers
188
BIOS Reset Source Register
188
Table 6-48 BIOS Reset Source Register
188
Reset Mask Register
189
Table 6-49 Reset Mask Register
189
BIOS IPMC Watchdog Timeout Register
190
BIOS Push Button Enable Register
190
Table 6-50 BIOS IPMC Watchdog Timeout Register
190
OS Reset Source Register
191
Table 6-51 BIOS Push Button Enable Register
191
Table 6-52 Reset Source Register
191
OS IPMC Watchdog Timeout Register
192
Table 6-53 os IPMC Watchdog Timeout Register
192
IPMC Watchdog Timeout Register
193
Table 6-54 IPMC Watchdog Timeout Register
193
IPMC Reset Source Register
194
Table 6-55 IPMC Reset Source Register
194
RTM SPI Interface Registers
195
Table 6-56 RTM SPI Address/Command Register
195
Table 6-57 RTM SPI Write Register
195
Interrupt Control and Status Registers
196
RTM Interrupt Status Register
196
External Interrupt Status Register
196
Table 6-58 RTM SPI Read Register
196
Table 6-59 External Interrupt Status Register
196
Processor Hot Status/Control Register
197
Table 6-60 Processor Hot Status/Control Register
197
Telecom Status/Control Register
198
Interrupt Mask and Map Registers
198
Table 6-61 Telecom Status/Control Register
198
Table 6-62 Address Map of Interrupt Mask and Map Registers
198
Table 6-63 Interrupt Mask and Map Registers
200
Flash Status and Protection Registers
201
Table 6-64 Flash Status Register
201
BIOS Boot Mode Register
202
Table 6-65 Default Boot SPI Flash Write Enable
202
Table 6-66 Recovery Boot SPI Flash Write Enable
202
Table 6-67 BIOS Boot Mode Register
202
SFMEM Module Configuration Register
203
Table 6-68 SFMEM Module Configuration Register
203
Update Channel Equalization Control Register
204
Table 6-69 Update Channel Equalization Control Register
204
IPMC E-Keying Status Register
205
IPMC E-Keying Control Register
205
Table 6-70 IPMC E-Keying Status Register
205
Table 6-71 IPMC E-Keying Control Register
205
IPMC GPIO Register
206
LED Status and Control Register
207
Table 6-73 LED Status and Control Register
207
NMI Status and Control Register
208
Telecom Clock Supervision Registers
208
Telecom Clocking Status Registers
208
Table 6-74 NMI Status and Control Register
208
Table 6-75 Telecom Backplane Clocking Status Register
208
Table 6-77 Telecom CH1_CLK1A Clock Period MSB Register
209
Table 6-78 Telecom CH1_CLK1A Clock Period LSB Register
209
Table 6-76 Telecom Backplane Clocking Latch Register
209
Telecom Timer Registers
210
Table 6-79 Telecom CH1_CLK1B Clock Period MSB Register
210
Table 6-80 Telecom CH1_CLK1B Clock Period LSB Register
210
Miscellaneous Status/Control Registers
211
Table 6-81 Telecom Timer MSB Register
211
Table 6-82 Telecom Timer LSB Register
211
Table 6-83 CPLD Version and Spare Signal Status Register
211
Scratch Registers
212
Table 6-85 IPMC Scratch Register
212
7 Serial over LAN
213
Overview
213
Installing the Ipmitool
213
Configuring SOL Parameters
214
Using Standard IPMI Commands
214
Using Ipmitool
215
Establishing a SOL Session
217
8 Supported IPMI Commands
219
Standard IPMI Commands
219
Global IPMI Commands
219
System Interface Commands
219
Table 8-1 Supported Global IPMI Commands
219
Table 8-2 Supported System Interface Commands
219
Watchdog Commands
220
Table 8-3 Supported Watchdog Commands
220
SEL Device Commands
221
FRU Inventory Commands
221
Table 8-4 Supported SEL Device Commands
221
Table 8-5 Supported FRU Inventory Commands
221
Sensor Device Commands
222
Table 8-6 Supported Sensor Device Commands
222
Chassis Device Commands
223
System Boot Options Commands
223
Table 8-7 Supported Chassis Device Commands
223
Table 8-8 Configurable System Boot Option Parameters
223
Table 8-9 System Boot Options Parameter #96
224
Table 8-10 System Boot Options Parameter #97
225
Table 8-11 System Boot Options Parameter #98
226
Table 8-12 System Boot Options - Parameter #100 - Data Format
227
Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview
227
Table 8-13 System Boot Options Parameter #100 - SET Command Usage
228
Table 8-14 System Boot Options Parameter #100 - GET Command Usage
229
Table 8-15 System Boot Options Parameter #100 - Supported Parameters
230
Table 8-16 Boot_Order Devices
231
LAN Device Commands
233
PICMG 3.0 Commands
233
Table 8-17 Supported LAN Device Commands
233
Table 8-18 Supported PICMG 3.0 Commands
233
Set/Get Power Level
235
Artesyn Specific Commands
235
Serial Output Commands
236
Set Serial Output Command
236
Table 8-19 Serial Output Commands
236
Table 8-20 Request Data of Set Serial Output Command
236
Get Serial Output Command
237
Table 8-21 Response Data of Set Serial Output Command
237
Table 8-22 Request Data of Get Serial Output Command
238
Table 8-23 Response Data of Get Serial Output Command
238
Pigeon Point Specific Commands
239
Table 8-24 Pigeon Point Extension Commands
239
Get Status Command
240
Table 8-26 Get Status Command Description
240
Get Serial Interface Properties Command
243
Table 8-27 Get Serial Interface Properties Command Description
243
Set Serial Interface Properties Command
244
Table 8-28 Set Serial Interface Properties Command Description
244
Get Debug Level Command
245
Table 8-29 Get Debug Level Command Description
245
Set Debug Level Command
246
Table 8-30 Set Debug Level Command Description
246
Get Hardware Address Command
247
Set Hardware Address Command
247
Table 8-31 Get Hardware Address Command Description
247
Table 8-32 Set Hardware Address Command Description
247
Get Handle Switch Command
248
Table 8-33 Get Handle Switch Command Description
248
Get Payload Communication Time-Out Command
249
Set Handle Switch Command
249
Table 8-34 Set Handle Switch Command Description
249
Table 8-35 Get Payload Communication Time-Out Command Description
249
Set Payload Communication Time-Out Command
250
Table 8-36 Set Payload Communication Time-Out Command Description
250
Disable Payload Control Command
251
Enable Payload Control Command
251
Table 8-37 Enable Payload Control Command Description
251
Table 8-38 Disable Payload Control Command Description
251
Hang IPMC Command
252
Reset IPMC Command
252
Table 8-39 Reset IPMC Command Description
252
Table 8-40 Hang IPMC Command Description
252
Graceful Reset Command
253
Table 8-41 Graceful Reset Command Description
253
Get Payload Shutdown Time-Out Command
254
Table 8-42 Get Payload Shutdown Time-Out Command Description
254
Get Module State Command
255
Set Payload Shutdown Time-Out Command
255
Table 8-43 Set Payload Shutdown Time-Out Command Description
255
Table 8-44 Get Module State Command Description
255
Disable Module Site Command
257
Enable Module Site Command
257
Table 8-45 Enable Module Site Command Description
257
Table 8-46 Disable Module Site Command Description
257
Reset Carrier SDR Repository Command
258
Table 8-47 Reset Carrier SDR Repository Command Description
258
9 FRU Information and Sensor Data Records
259
FRU Information
259
Table 9-1 FRU Information
259
MAC Address Record
260
Table 9-2 Artesyn MAC Addresses Record
260
Table 9-3 Artesyn MAC Address Descriptor
260
E-Keying
261
Table 9-4 Interface Type Assignments
261
Table 9-5 Contents of the Blade Point-To-Point Connectivity Record Area
262
FRU Information and Sensor Data
263
Power Configuration
264
Sensor Data Records
264
Table 9-6 Power Configuration
264
Table 9-7 IPMI Sensors Overview
264
FRU Information and Sensor Data
266
Figure 9-1 Location of Temperature Sensors
267
Table 9-8 Sensor Data Records
268
FRU Information and Sensor Data
269
FRU Information and Sensor Data
270
FRU Information and Sensor Data
271
FRU Information and Sensor Data
272
FRU Information and Sensor Data
273
FRU Information and Sensor Data
274
10 Firmware Upgrade
275
HPM.1 Firmware Upgrade
275
Overview
275
Installing the Ipmitool
275
Update Procedure
275
Interface
276
KCS Interface
276
Ipmb-0
276
IPMI over LAN (BASE)
276
IPMC Upgrade
277
Figure 10-1 IPMC Component Elements
277
BIOS/FPGA Upgrade
278
Figure 10-2 SPI Bus Connection
279
Upgrade Package
280
Table 10-1 HPM Upgrade Package
280
Replacing Battery
281
Replacing the Battery
281
Figure A-1 Location of On-Board Battery
281
Related Documentation
285
Artesyn Embedded Technologies - Embedded Computing Documentation
285
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications
285
Manufacturers' Documents
286
Related Specifications
286
Table B-2 Manufacturer's Documents
286
Table B-3 Related Specifications
286
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