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Manuals and User Guides for Artesyn Embedded Technology ATCA-7490. We have
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Artesyn Embedded Technology ATCA-7490 manual available for free PDF download: Installation And Use Manual
Artesyn Embedded Technology ATCA-7490 Installation And Use Manual (372 pages)
Brand:
Artesyn Embedded Technology
| Category:
Server
| Size: 6 MB
Table of Contents
Table of Contents
3
About this Manual
23
Table
28
Safety Notes
29
Sicherheitshinweise
33
1 Introduction
39
Features
39
Standard Compliances
40
Table 1-1 Standard Compliances
40
Mechanical Data
41
Product Identification
42
Figure 1-1 Location of Serial Number and QR Code
42
Ordering Information
43
Blade Variants
43
2 Hardware Preparation and Installation
45
Unpacking and Inspecting the Blade
45
Environmental and Power Requirements
46
Environmental Requirements
46
Table 2-1 Environmental Requirements
47
Table
48
Figure 2-1 Location of Critical Temperature Spots (Blade - Top Side)
49
Power Requirements
50
Table 2-2 Power Requirements
50
Table 2-3 Power Consumption of ATCA-7490 with and Without RTM
51
Blade Layout
52
Figure 2-2 ATCA-7490 Blade Layout
52
Switch Settings
53
Figure 2-3 Switch Location (Bottom Side of the Blade)
53
Installing the Blade Accessories
55
DIMM Memory Modules
55
DIMM Sockets
56
SSD Carrier and MO297 SSD Modules
58
Installing and Removing the Blade
60
Installing the Blade
61
Removing the Blade
64
3 Controls, Indicators, and Connectors
67
Faceplate
67
Leds
68
Faceplate Leds
68
Reset Button
69
Connectors
69
Serial Interface Connector
70
Table 3-2 RJ45 Female Serial Console Connector Pinout
70
Figure 3-2 Serial Interface Connector Pinout
70
Ethernet Connector
71
USB Connectors
71
Figure 3-3 Ethernet Interface Connectors Pinout
71
IPMC Debug Console Connector P9
72
Figure 3-4 USB Connector Pinout
72
Figure 3-5 IPMC Debug Console Connector P9 Pinout
72
On-Board Connectors
73
MO297 SSD Module Carrier Connector
73
Figure 3-6 Location of MO297 SSD Module Connector
74
Table 3-3 Signal Segment Pinout
75
Table 3-4 Power Segment Pinout
75
Figure 3-7 MO297 SSD Module Carrier Connector Pinout
75
Advancedtca Backplane Connectors
77
Figure 3-8 Location of Advancedtca Connectors
77
Figure 3-9 P10 Backplane Connector Pinout
78
Figure 3-10 P20 Backplane Connector Pinout - Rows a to D
79
Figure
80
Figure 3-11 P20 Backplane Connector Pinout - Rows E to H
80
Figure 3-12 P22 Backplane Connector Pinout - Rows a to D
80
Figure 3-13 P22 Backplane Connector Pinout - Rows E to H
81
Figure 3-14 P23 Backplane Connector Pinout - Rows a to D
81
Figure 3-15 P23 Backplane Connector Pinout - Rows E to H
82
Figure 3-16 P30 Backplane Connector Pinout - Rows a to D
83
Figure 3-17 P30 Backplane Connector Pinout - Rows E to H
83
Figure 3-18 P31 Backplane Connector Pinout - Rows a to D
84
Figure 3-19 P31 Backplane Connector Pinout - Rows E to H
84
Figure 3-20 P32 Backplane Connector Pinout - Rows a to D
85
Figure 3-21 P32 Backplane Connector Pinout - Rows E to H
85
Table 3-5 P40 Backplane Connector Pinout
86
Figure 3-22 P33 Backplane Connector Pinout - Rows a to D
86
Figure 3-23 P33 Backplane Connector Pinout - Rows E to H
86
4 Functional Description
89
Block Diagram
89
Figure 4-1 ATCA-7490 Block Diagram
89
Processor
90
DDR4 Main Memory
90
Platform Controller Hub Intel C612 Wellsburg
91
PCH I/O Controller Features
92
Intel I350 Quad GB Ethernet Controller
93
Firmware Flashes
93
ATCA Fabric if Ethernet
93
Storage Controller
94
ATCA Update Channels
94
Table 4-1 P20 Backplane Connector Pinout
94
MO297 Slimsata Embedded Solid State Disc (SSD) Carrier/Riser Card
96
Heat Sink
96
Bios
96
Ipmc
96
I2C Bus
97
Table 4-2 IPMI I2C Bus Address Map (Private I2C Bus)
97
Figure 4-2 Master Only I2C Bus Architecture
97
FRU Data Serial IDROM
98
Table
98
System Event Log EEPROM
99
Serial Redirection
99
Serial over LAN
99
Control Logic
100
Front Board Faceplate
100
Faceplate Serial Interfaces
100
IPMC Debug Console
101
Table 4-3 Faceplate Serial Interfaces
101
Table 4-4 IPMC Debug Console Destination Selection
101
USB Interfaces
102
LPC Interface
102
Trusted Platform Module
102
Real Time Clock
103
Smbus
103
Figure 4-3 Smbus Architecture
104
5 Maps and Registers
107
FPGA Registers
107
Table 5-2 Register Access Type
107
Register Decoding
108
LPC Decoding
108
Table 5-3 LPC I/O Register Map Overview
108
I2C Register Decoding
109
POST Code Register
109
Table 5-4 IPMC I2C Register Map
109
Super IO Configuration Register
110
Entering the Configuration State
110
Existing the Configuration State
110
Table 5-6 Super IO Configuration Index Register
110
Table 5-7 Super IO Configuration Data Register
110
Configuration Mode
111
Super IO Configuration Registers
111
Table 5-8 Global Configuration Register Summary
111
Table 5-9 Super IO Logical Device Number Register
112
Table 5-10 Super IO Device Identification Register
112
Table 5-11 Super IO Device Revision Register
112
Table 5-12 Super IO LPC Control Register
113
Table 5-13 Global Super IO SERIRQ and Pre-Divide Control Register
113
Table 5-14 Logical Device Configuration Register Summary
114
Table 5-15 Logical Device Enable Register
114
Table 5-18 Logical Device Common Decode Ranges
115
Table 5-16 Logical Device Base IO Address MSB Register
115
Table 5-17 Logical Device Base IO Address LSB Register
115
Table 5-19 Logical Device Primary Interrupt Register
116
UART1 and UART2 Register Map
117
UART Register Overview
117
Table 5-20 Logical Device 0X74 Reserved Register
117
Table 5-21 Logical Device 0X75 Reserved Register
117
Table 5-22 Logical Device 0Xf0 Reserved Register
117
UART Registers DLAB=0
118
Table 5-23 UART Register Overview
118
Table 5-24 Receiver Buffer Register (RBR) if DLAB=0
118
Table 5-25 Transmitter Holding Register (THR) if DLAB=0
119
Table 5-26 Interrupt Enable Register (IER), if DLAB=0
119
Table 5-27 UART Interrupt Priorities2
120
Table 5-28 Interrupt Identification Register (IIR)
120
Table 5-29 Interrupt Identification Register Decode
121
Table 5-30 FIFO Control Register (FCR)
122
Table 5-31 Line Control Register (LCR)
123
Table 5-32 Modem Control Register (MCR)
125
Table 5-33 Line Status Register (LSR)
127
Table 5-34 Modem Status Register (MSR)
130
Programmable Baud Rate Generator
131
Table 5-35 Scratch Register (SCR)
131
Table 5-36 Divisor Latch LSB Register (DLL), if DLAB=1
132
Table 5-37 Divisor Latch MSB Register (DLM), if DLAB=1
132
FPGA Register Mapping
133
LPC I/O Register Map
133
IPMC I2C Register Map
133
Table 5-38 FPGA Register Map Overview
133
Module Identification Register
137
Serial Redirection Control Register
137
Table 5-39 Module Identification Register
137
Table 5-40 FPGA Version Register
137
Version Register
137
Serial over LAN (SOL) Control Register
138
Table 5-41 Serial Redirection Control Register
138
Table 5-42 Serial over LAN Control Register
138
Serial Line Routing Register
139
Table 5-43 Serial Line Routing Register
139
IPMC Power Failure Registers
140
ME Power Failure Registers
140
Table 5-44 IPMC Power Level Register
140
Table 5-45 IPMC Power Level Multiplier Register
140
Table
141
Table 5-46 ME Power Failure State Register
141
Table 5-47 ME Power Failure States
141
Payload Power Failure Registers
142
Table 5-48 ME Power Failure Cause Register
142
Table 5-49 Payload Power Failure State Register
142
Table
143
Table 5-50 Payload Power Failure States
143
Table
144
Table 5-51 Payload Power Failure Cause Register 1
145
Table 5-52 Payload Power Failure Cause Register 2
146
Table 5-53 Payload Power Failure Cause Register 3
147
Power Status Register
148
ARTM Power Failure Register
148
Table 5-54 Power Status Register
148
Table 5-55 ARTM Power Failure Register
148
IPMC Power Level Multiplier Register
140
IPMC Power Level Register
140
Reset Registers
149
BIOS Reset Source Register
149
Table 5-56 ARTM Power Failure States
149
Reset Mask Register
150
Table 5-57 BIOS Reset Source Register
150
BIOS IPMC Watchdog Timeout Register
151
Table 5-59 BIOS IPMC Watchdog Timeout Register
151
BIOS Push Button Enable Register
152
OS Reset Source Register
152
Table 5-60 BIOS Push Button Enable Register
152
OS IPMC Watchdog Timeout Register
153
Table 5-61 os Reset Source Register
153
IPMC Watchdog Timeout Register
154
Table 5-62 os IPMC Watchdog Timeout Register
154
Table 5-63 IPMC Watchdog Timeout Register
154
IPMC Reset Source Register
155
Table 5-64 IPMC Reset Source Register
155
IPMC Interrupt Status Register
156
Table 5-65 IPMC Interrupt Status Register
156
10DIMM ADR Configuration Register
157
Table 5-66 DIMM ADR Feature Configuration Register
157
11DIMM ADR Status Register
158
12Reset Control Register
158
Table 5-67 DIMM ADR Status Register
158
Table 5-68 Reset Control Register
158
CPU Control Register
159
Table 5-69 CPU Control Register
159
NMI Control Status Registers
160
Table 5-70 S-States Control Register
160
NMI Generation Register
161
NMI Interrupt Status Register
161
S-States Control Register
160
Interrupt Control and Status Registers
161
Table 5-71 NMI Generation Register
161
Table 5-72 NMI Interrupt Status Register
161
Internal Interrupt Status Register
162
Table 5-73 Internal Interrupt Status Register
162
Table 5-74 Telecom Interrupt Status Register
162
Telecom Interrupt Status Register
162
External Interrupt Status Register
163
RTM Interrupt Status Register
163
Table 5-75 Telecom Interrupt Control Register
163
Table 5-76 External Interrupt Status Register
163
Telecom Interrupt Control Register
163
Interrupt Mask and Map Registers
164
Table 5-77 Address Map of Interrupt Mask and Map Registers
164
Table
165
Table 5-78 Interrupt Mask and Map Registers
165
PCI Express Hot Plug I2C IO Expander Registers
166
CPU0 Hot Plug I2C IO Expander Registers
166
CPU1 Hot Plug I2C IO Expander Registers
166
Hot-Plug Virtual Pin Port Registers
166
Table 5-79 Hot-Plug Virtual Pin Port Register
166
PCA9555 Internal Register Access
168
Flash Status and Selection Registers
168
Table 5-80 Address Control for PCA9555 Internal Register
168
Table 5-81 Content of PCA9555 Internal Register
168
Table 5-82 Flash Status Register
169
PCH Output Enable Register
170
RTM SPI Interface Registers
170
Table 5-83 PCH Output Enable Register
170
Table 5-84 RTM SPI Address/Command Register
171
Table 5-85 RTM SPI Write Register
171
RTM USB Control Register
172
Table 5-87 Update Channel Equalization Control Register
172
Table 5-88 RTM USB Control Register
172
Table 5-89 RTM Status Register
172
Update Channel Equalization Control Register
172
LED Status and Control Register
173
Table 5-90 RTM Interrupt Status Register
173
Table 5-91 LED Control Register
173
CPU Presence Detection Register
174
Spare Signals Status Registers
174
Table 5-92 Spare Signal Status Register
174
Table 5-93 CPU Presence Detection Register
174
CPU Error Status Register
175
Table 5-94 CPU Error Status Register
175
Table 5-95 Supervised Telecom Clocks Reference List
175
Telecom Clock Supervision Registers
175
Table 5-96 Telecom Clock Monitor Control Register
176
Table 5-97 Telecom Clock Monitor Status Register
176
Table 5-98 Telecom Clock Monitor out of Range Register
177
Table 5-99 Telecom Clock Monitor Select Register
177
Table 5-100 Telecom Clock Monitor Time Base Register
178
Table 5-101 Telecom Clock Monitor Frequency/Period Register
179
Table 5-102 Telecom Clock Monitor Lower Limit Register
179
BIOS Version Registers
180
Table 5-103 Telecom Clock Monitor Upper Limit Register
180
Table 5-104 BIOS Version Register 1
180
Table 5-105 BIOS Version Register 2
180
Table 5-106 BIOS Version Register 3
180
IPMC BIOS Communication Registers
181
Scratch Registers
181
Table 5-107 IPMC BIOS Communication Register 1
181
Table 5-108 IPMC BIOS Communication Register 2
181
Table 5-109 IPMC BIOS Communication Register 3
181
Table 5-110 LPC Scratch Register
181
Table 5-111 IPMC Scratch Register
182
6 Bios
183
Accessing the Blade Using the Serial Console Redirection
184
Requirements for Serial Console Redirection
184
Default Access Parameters
184
Connecting to the Blade
185
Changing Configuration Settings
185
Boot Support
187
Boot Mode
187
Boot Type
187
Supported Boot Devices
188
Selecting the Boot Device
188
Figure 6-2 Boot Device Priority
189
By Boot Menu
190
SATA RAID Configuration
191
RAID Features
191
RAID Configuration
192
Enabling RAID Mode in BIOS
192
RAID Configuration for Legacy Boot Type
192
Figure 6-4 Intel Rapid Store Technology Option ROM Prompt
192
Figure 6-5 Intel Rapid Store Technology Option ROM Main Menu
193
Figure 6-6 Intel Rapid Store Technology Option ROM Create Volume Menu
193
RAID Configuration for UEFI Boot Type
194
Figure 6-7 Device Manager
195
Figure 6-8 Intel Rapid Store Technology Main Menu
196
Figure 6-9 Intel Rapid Store Technology Create Volume Menu
196
Iscsi Boot
197
Table 6-1 Iscsi Configuration Menu
198
Table 6-2 Add an Iscsi Attempt Menu
200
IPMI Boot Parameter
202
Figure 6-10 IPMI Boot Parameter
202
BIOS Setup Configuration
203
Main
204
Figure 6-11 Main Menu Options
204
Advanced
205
Figure 6-12 Platform Information
205
Table 6-4 Advanced >> RTM Configuration
206
Figure 6-13 RTM Configuration
206
Table
207
Table
208
Table 6-5 Advanced >> Peripheral Configuration
209
Figure 6-14 Peripheral Configuration
209
Table 6-6 Advanced >> Peripheral Configuration >> Intel VT for Directed I/O (VT-D)
210
Figure 6-15 Peripheral Intel VT Configuration
210
Table 6-7 Advanced >> SATA Configuration
212
Figure 6-16 SATA Configuration
212
Figure 6-17 USB Configuration
213
Table 6-8 Advanced >> USB Configuration
214
Table 6-9 Advanced >> Processor Configuration
215
Figure 6-18 Processor Configuration
215
Table 6-10 Advanced >> Processor Configuration >> Processor Power Management Configuration
217
Figure 6-19 Processor Power Management Configuration
217
Table 6-11 Advanced >> Memory Configuration
219
Figure 6-20 Memory Configuration
219
Figure 6-21 Memory RAS Configuration
220
Table 6-12 Advanced >> Memory Configuration >> Memory RAS Configuration
221
Table 6-13 Advanced >> Console Redirection
222
Figure 6-22 Console Redirection
222
Figure 6-23 APEI Configuration
223
Table 6-14 Advanced >> APEI Configuration
224
Figure 6-24 BIOS Event Log Configuration
225
Table 6-15 Advanced >> Memory Event Log Viewer
227
Figure 6-26 Memory Event Log Viewer
227
Table 6-16 Advanced >> IPMI Configuration
228
Figure 6-27 IPMI Configuration
228
Security
230
Boot
231
Figure 6-31 Legacy Boot Order
234
Exit
235
UEFI Secure Boot
236
Restoring BIOS Default Settings
237
Figure 6-33 Administer Secure Boot
237
IPMI Support
238
Watchdog Support
238
BIOS Error Logging
239
Runtime Error Logging
239
Table 6-20 Logged Error Events
239
IPMI Error Logging
240
Table 6-21 BIOS Supported IPMI Events
240
BIOS LED Usage
242
Upgrading the BIOS
243
BIOS POST Codes
243
7 Serial over LAN
251
Configuring SOL Parameters
251
Configuring Using Standard IPMI Commands
252
Configuration Using Ipmitool
253
Installing the Ipmitool
253
Establishing an SOL Session
258
8 Supported IPMI Commands
259
Standard IPMI Commands
259
Global IPMI Commands
259
System Interface Commands
259
Table 8-1 Supported Global IPMI Commands
259
Table 8-2 Supported System Interface Commands
259
Watchdog Commands
260
Table 8-3 Supported Watchdog Commands
260
SEL Device Commands
261
FRU Inventory Commands
261
Table 8-4 Supported SEL Device Commands
261
Table 8-5 Supported FRU Inventory Commands
261
Sensor Device Commands
262
Table 8-6 Supported Sensor Device Commands
262
Chassis Device Commands
263
System Boot Options Commands
263
Table 8-7 Supported Chassis Device Commands
263
Table 8-8 Configurable System Boot Option Parameters
263
Table 8-9 System Boot Options Parameter #96
264
Table 8-10 System Boot Options Parameter #98
265
Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview
266
Table 8-11 System Boot Options - Parameter #100 - Data Format
267
Table 8-12 System Boot Options Parameter #100 - SET Command Usage
267
Table 8-13 System Boot Options Parameter #100 - GET Command Usage
268
Table 8-14 System Boot Options Parameter #100 - Supported Parameters
270
Table 8-15 Boot Order Devices
277
LAN Device Commands
279
PICMG 3.0 Commands
279
Table 8-16 Supported LAN Device Commands
279
Table 8-17 Supported PICMG 3.0 Commands
279
Artesyn Specific Commands
281
Serial Output Commands
281
Set Serial Output Command
282
Table 8-18 Serial Output Commands
282
Table 8-19 Request Data of Set Serial Output Command
282
Get Serial Output Command
283
Table 8-20 Response Data of Set Serial Output Command
283
Table 8-21 Request Data of Get Serial Output Command
284
Table 8-22 Response Data of Get Serial Output Command
284
OEM Command to Configure IPMI Features
285
Table 8-23 Feature Configuration Command
285
Set Feature Configuration
286
Table 8-24 Set Feature Configuration Command
286
Get Feature Configuration
287
Table 8-25 Feature Selector Assignments
287
Table 8-26 Get Feature Configuration Command
287
Pigeon Point Specific Commands
288
Table 8-27 Pigeon Point Extension Commands
288
Get Status Command
290
Table 8-29 Get Status Command Description
290
Reset IPMC Command
292
Table 8-30 Reset IPMC Command Description
292
Get Serial Interface Properties Command
293
Table 8-31 Get Serial Interface Properties Command Description
293
Set Serial Interface Properties Command
294
Table 8-32 Set Serial Interface Properties Command Description
294
Get Debug Level Command
295
Table 8-33 Get Debug Level Command Description
295
Set Debug Level Command
296
Table 8-34 Set Debug Level Command Description
296
Get Hardware Address Command
298
Set Hardware Address Command
298
Table 8-35 Get Hardware Address Command Description
298
Table 8-36 Set Hardware Address Command Description
298
Get Handle Switch Command
299
Table 8-37 Get Handle Switch Command Description
299
Get Payload Communication Time-Out Command
300
Set Handle Switch Command
300
Table 8-38 Set Handle Switch Command Description
300
Table 8-39 Get Payload Communication Time-Out Command Description
300
Set Payload Communication Time-Out Command
301
Table 8-40 Set Payload Communication Time-Out Command Description
301
Disable Payload Control Command
302
Enable Payload Control Command
302
Table 8-41 Enable Payload Control Command Description
302
Table 8-42 Disable Payload Control Command Description
302
Graceful Reset Command
303
Hang IPMC Command
303
Table 8-43 Hang IPMC Command Description
303
Table 8-44 Graceful Reset Command Description
303
Get Payload Shutdown Time-Out Command
304
Table 8-45 Get Payload Shutdown Time-Out Command Description
304
Get Module State Command
305
Set Payload Shutdown Time-Out Command
305
Table 8-46 Set Payload Shutdown Time-Out Command Description
305
Table 8-47 Get Module State Command Description
305
Disable Module Site Command
307
Enable Module Site Command
307
Table 8-48 Enable Module Site Command Description
307
Table 8-49 Disable Module Site Command Description
307
Reset Carrier SDR Repository Command
308
Table 8-50 Reset Carrier SDR Repository Command Description
308
9 IPMI Feature Set
309
Figure 9-1 IPMC Block Diagram of ATCA-7490
311
Firmware Architecture
312
Firmware Upgrade
313
HPM.1 Components
313
Figure 9-2 Firmware Architecture
313
IPMI Boot-Loader and Firmware Component
314
Table 9-1 HPM.1 Components
314
FPGA Component
315
IAP Component
315
BIOS Component
316
Retrieving Version Information
316
Firmware Upgrade Tool
318
Installing Ipmitool
318
Updating Ipmitool
319
Upgrade Interfaces
319
HPM.2 Specific Firmware Updates
320
Sensors
322
Table 9-2 ATCA-7490 Specific Sensors
322
Figure 9-3 Temperature Sensors Location
336
Payload Driven Sensors
336
Boot Bank Supervision Sensor
337
Table 9-3 Event Data of Boot Bank Sensor
337
IPMC POST Results Sensor
338
Power Good Sensor
338
Power Interface Sensors
338
Table 9-4 Status Sensor's Sensor Reading
338
Reset Cause Sensor
339
Table 9-5 Voltage and Temperature Sensor Devices
339
Voltage and Temperature Sensor
339
ME Power Failure Sensor
340
Payload Power Failure State Sensor
340
Payload Power Failure Cause Sensor
341
Post
341
Ejector Handle De-Bounce
342
FRU Inventory
342
Table 9-6 FRU Information and SEL at EEPROM Storage
342
MAC Address FRU OEM Records
343
Table 9-7 Artesyn MAC Address Record
343
Table 9-8 Artesyn MAC Address Descriptor
343
Table 9-9 Interface Type Assignments
344
Power Configuration
345
Reset and Power Domain
345
Table 9-10 Power Consumption Depending on the Product Version
345
BIOS Boot Configuration Parameters
346
Table 9-11 IPMC Boot Parameter Storage Format
346
Asynchronous Event Notification
347
Serial Line Selection
347
BIOS Boot Bank Selection
348
Boot Bank Sensor
348
Fail Safe Logic
349
Glue Logic FPGA Flash Selection
351
Boot Bank Sensor
352
Fail Protect Logic
352
Remote Crisis Recover Mode
354
Settable Graceful Shutdown Timeout
354
Local System Event Log (SEL)
355
Replacing the Battery
357
Figure A-1 Location of On-Board Battery
357
ATCA-7490 Declassification Procedure
361
ATCA-7490 Non-Volatile Memory Statement
361
Table B-1 ATCA-7490 Nonvolatile Memory
361
B.1 ATCA-7490 Non-Volatile Memory Statement
361
SPI Flash - Processor
362
SPI Flash - IPMC
364
USER Parameters
365
FPGA Configuration Flash
366
Ipmc I2C Eeprom
367
Related Documentation
369
Artesyn Embedded Technologies - Embedded Computing Documentation
369
Table C-1 Artesyn Embedded Technologies - Embedded Computing Publications
369
Manufacturers' Documents
370
Related Specifications
370
Table C-2 Manufacturer's Documents
370
Table C-3 Related Specifications
370
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