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ATCA-7360
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Artesyn ATCA-7360 manual available for free PDF download: Installation And Use Manual
Artesyn ATCA-7360 Installation And Use Manual (288 pages)
Brand:
Artesyn
| Category:
Single board computers
| Size: 3 MB
Table of Contents
Table of Contents
3
About this Manual
19
Table 6-7 Table
24
Faceplate
25
Figure
25
Table
25
Safety Notes
27
Sicherheitshinweise
31
1 Introduction
37
Features
37
Standard Compliances
38
Table 1-1 Standard Compliances
38
Mechanical Data
39
Ordering Information
40
Table 1-3 Blade Variants - Ordering Information
40
Table 1-4 Blade Accessories - Ordering Information
40
Product Identification
42
Figure 1-1 Serial Number Location
42
2 Installation
45
Unpacking and Inspecting the Blade
45
Environmental and Power Requirements
46
Environmental Requirements
46
Table 2-1 Environmental Requirements
47
Table 2-2 Critical Temperature Limits
48
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)
49
Power Requirements
50
Table 2-3 Power Requirements
50
Blade Layout
52
Figure 2-2 ATCA-7360 Blade Layout
52
Switch Settings
53
Table 2-4 Switch Settings
54
Installing Blade Accessories
55
DIMM Memory Modules
56
PMEM and SATA Module
57
USB 2.0 Flash Module
59
Installing and Removing the Blade
60
Installing the Blade
61
Removing the Blade
64
3 Controls, Indicators, and Connectors
67
Mechanical Layout
67
Figure 3-1 Mechanical Layout
67
Faceplate
68
Leds
69
Figure 3-3 Location of Faceplate Leds
69
Table 3-1 Faceplate Leds
70
Keys
71
Figure 3-4 Location of Faceplate Reset Key
71
Connectors
72
Ethernet Connector
72
Figure 3-5 Location of Ethernet Connector
72
Figure 3-6 Ethernet Interface Connectors Pinout
73
Figure 3-7 Location of Serial Connector
73
Serial Interface Connector
73
Figure 3-8 Serial Interface Connector Pinout
74
Figure 3-9 Location of USB Connectors
74
USB Connectors
74
On-Board Connectors
75
PMEM/SFMEM Module Connector
75
Figure 3-10 USB Connector Pinout
75
Figure 3-11 Location of PMEM/SFMEM Module Connector
76
Figure 3-12 PMEM/SATA Module Connector Pinout
77
USB Flash Module Connector
78
Figure 3-13 Location of USB Flash Module Connector
78
Figure 3-14 USB Flash Module Connector Pin Assignment
79
Advancedtca Backplane Connectors
80
Figure 3-15 Location of Advancedtca Connectors
80
Figure 3-16 P10 Backplane Connector Pinout
81
Figure 3-17 P20 Backplane Connector Pinout - Rows a to D
82
Figure 3-18 P20 Backplane Connector Pinout - Rows E to H
83
Figure 3-19 P23 Backplane Connector Pinout - Rows a to D
83
Figure 3-20 P23 Backplane Connector Pinout - Rows E to H
84
Figure 3-21 P30 Backplane Connector Pinout - Rows a to D
85
Figure 3-22 P30 Backplane Connector Pinout - Rows E to H
85
Figure 3-23 P32 Backplane Connector Pinout - Rows a to D
86
Figure 3-24 P32 Backplane Connector Pinout - Rows E to H
86
4 Bios
87
Introduction
87
Accessing the Blade Using the Serial Console Redirection
88
Requirements for Serial Console Redirection
88
Table 4-1 BIOS Key Codes for Terminal Emulation Program
88
Default Access Parameters
89
Connecting to the Blade
89
Changing Configuration Settings
89
Main Menu
90
Boot Options
91
Selecting the Boot Device
91
Supported Boot Devices
91
By Boot Selection Menu
93
Figure 4-3 Option ROM Execution
94
Iscsi Setup for Base and Fabric Ethernet
94
Figure 4-4 Iscsi Port Selection
95
ISCSI Port Selection
95
Table 4-2 Ethernet Port Mapping
95
Figure 4-5 Iscsi Port Configuration
96
Iscsi Port Configuration
96
Table 4-3 Select Iscsi Boot Priority Hot Keys
96
Figure 4-6 Iscsi Boot Configuration
97
Iscsi Boot Configuration
97
Figure 4-7 Iscsi CHAP Configuration
98
Iscsi Challenge Handshake Authentication Protocol (CHAP) Configuration
98
BIOS Setup Configuration
99
Advanced
99
Advanced -> CPU Configuration
99
Main
99
Table 4-5 CPU Configuration
99
Advanced -> Memory Configuration
101
Table 4-6 Memory Configuration
101
Advanced -> Chipset - North Bridge
102
Table 4-7 Chipset - North Bridge
102
Table 4-24 Table
103
Table 4-8 Chipset - North Bridge -> Intel (R) VT for Directed I/O Configuration
103
Table 4-9 Chipset - North Bridge -> IOH Thermal Sensors
103
Advanced -> Chipset - South Bridge
104
Table 4-10 Chipset - South Bridge
104
Table 4-11 Chipset - South Bridge -> USB Configuration
104
Advanced -> SATA Configuration
105
Advanced -> USB Configuration
105
Table 4-12 Advanced -> SATA Configuration
105
Table 4-13 Advanced -> USB Configuration
105
Advanced -> Super IO Configuration
106
Table 4-14 Super IO Configuration -> Serial Port 0 Configuration
106
Advanced -> Serial Port Console Redirection
107
Table 4-15 Advanced -> Serial Port Console Redirection
107
Table 4-16 Serial Port Console Redirection -> Console Redirection Settings
107
Advanced -> Runtime Error Logging
108
Advanced -> UEFI Network Stack
108
Table 4-17 Advanced -> UEFI Network Stack
108
Table 4-18 Advanced -> Runtime Error Logging
108
Advanced -> SMBIOS Event Log
109
Table 4-19 SMBIOS Event Log -> SMBIOS Event Log Settings
109
Advanced -> Local IPMI System Event Log
110
Advanced -> WHEA Configuration
110
Ipmi
110
IPMI -> IPMI Watchdog Configuration
110
Table 4-20 Advanced -> Local IPMI System Event Log
110
Table 4-21 Advanced -> WHEA Configuration
110
Table 4-22 IPMI -> IPMI Watchdog Configuration
110
IPMI -> System Event Log
111
Iscsi
111
Table 4-23 IPMI -> System Event Log
111
Table 4-24 Iscsi
112
Boot
113
Boot -> Option ROM Execution
113
Table 4-26 Boot -> Option ROM Execution
113
Security
114
Save & Exit
114
CPU Performance Settings
115
Memory Configuration
115
Independent Channel Mode
116
Spare Channel Mode
116
Mirrored Channel Mode
116
Lockstep Channel Mode
117
Restoring BIOS Default Settings
117
Shelf Slot Power Requirement
118
LED Usage
118
Upgrading the BIOS
118
BIOS Error Logging
119
Runtime Error Logging
119
Error Simulation
120
Table 4-28 Logged Error Events
120
IPMI Error Logging
122
Table 4-29 BIOS Supported IPMI Events
122
SMBIOS Error Logging
124
Multi-Bit ECC Memory Error
125
Single-Bit ECC Memory Error
125
Table 4-30 Single-Bit ECC Memory Error Event Format
125
Table 4-31 Memory Information Definition
125
Table 4-32 Multi-Bit ECC Memory Error Event Format
125
POST Error
126
Table 4-33 Memory Information Definition
126
Table 4-34 POST Error Event Format
126
Table 4-35 Result First DWORD Supported POST Errors
127
Table 4-36 Result Second DWORD Supported POST Errors
127
PCI Parity Error
128
Table 4-37 PCI Parity Error Event Format
128
Table 4-38 PCI Information Definition
128
CPU Failure
129
PCI System Error
129
Table 4-39 Multi-Bit ECC Memory Error Event Format
129
Table 4-40 Memory Information Definition
129
Table 4-41 CPU Failure Event Format
129
Correctable Memory Log Disabled
130
Log Area Reset/Cleared
130
Table 4-42 Correctable Memory Log Disabled Event Format
130
Table 4-43 Memory Information Definition
130
Table 4-44 Log Area Reset/Cleared Event Format
130
10OEM Event EFI Status Code
131
System Boot
131
Table 4-45 System Boot Event Format
131
Table 4-46 System Boot Event Format
131
Table 4-47 Status Code Type Definition
132
Table 4-48 Status Code Value Definition
132
Table 4-50 Subclass EFI_COMPUTING_UNIT_CHIPSET (06H)
132
BIOS Status Codes
133
Table 4-51 Subclass EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (02H) (IPMI)
133
Standard Status Codes
134
Status Code Ranges
134
Table 4-52 Status Code Ranges
134
Table 4-54 PEI Status Codes
135
Table 4-55 DXE Status Codes
137
5 Functional Description
141
Block Diagram
141
Figure
141
Processor
142
Memory
142
Persistent Memory
143
Chipset
143
I/O Controller
143
Firmware Flashes
144
Ethernet Ports
145
Storage Controller
145
Embedded Flash Disk
145
Table 5-1 Ethernet Controller Types
145
SATA Embedded Flash Solid State Disc (SSD)
146
Bios
146
Ipmc
146
Serial Redirection
147
Serial over LAN
147
Control Logic
148
Front Board Faceplate
148
USB 2.0 Interface
149
Smbus Interface
149
Table
149
Real Time Clock
150
6 Maps and Registers
151
Interrupt Structure
151
Figure 6-1 Interrupt Structure on ATCA-7360
151
Table 6-1 Non-APIC (PIC Mode / 8259 Mode) Interrupt Mapping
152
Table 6-2 APIC Mode Interrupt Mapping
152
PCI Express Port Mapping
154
Registers
154
Table
154
Figure
154
Figure 6-2 IOH36D Pcie Port Mapping on ATCA-7360
154
Table 6-3 Pciexpress Port Mapping
154
Register Decoding
155
Table 6-5 Register Access Type
155
LPC Decoding
156
Table 6-6 LPC I/O Register Map Overview
156
POST Code Register
157
SPI Register Decoding
157
Super IO Configuration Register
158
Configuration Mode
158
Entering the Configuration State
158
Table 6-10 Super IO Configuration Data Register
158
Table 6-9 Super IO Configuration Index Register
158
Super IO Configuration Registers
159
Table 6-11 Global Configuration Register Summary
159
Table 6-12 Super IO Logical Device Number Register
160
Table 6-13 Super IO Device Identification Register
160
Table 6-14 Super IO Device Revision Register
160
Table 6-15 Super IO LPC Control Register
160
Table 6-16 Global Super IO SERIRQ and Pre-Divide Control Register
161
Table 6-17 Logical Device Configuration Register Summary
161
Table 6-18 Logical Device Enable Register
162
Table 6-19 Logical Device Base IO Address MSB Register
162
Table 6-20 Logical Device Base IO Address LSB Register
162
Table 6-21 Logical Device Common Decode Ranges
163
Table 6-22 Logical Device Primary Interrupt Register
163
UART1 and UART2 Register Map
164
Table 6-23 Logical Device 0X74 Reserved Register
164
Table 6-24 Logical Device 0X75 Reserved Register
164
Table 6-25 Logical Device 0Xf0 Reserved Register
164
UART Register Overview
164
Table 6-26 UART Register Overview
165
Table 6-35 Line Control Register (LCR)
165
Table 6-27 Receiver Buffer Register (RBR) if DLAB=0
166
Table 6-28 Transmitter Holding Register (THR) if DLAB=0
166
UART Registers DLAB=0
166
Table 6-29 Interrupt Enable Register (IER), if DLAB=0
167
Table 6-30 UART Interrupt Priorities
168
Table 6-31 Interrupt Identification Register (IIR)
168
Table 6-32 FIFO Control Register (FCR)
169
Table 6-33 Line Control Register (LCR)
170
Table 6-34 Modem Control Register (MCR)
172
Table 6-36 Modem Status Register (MSR)
177
Table 6-37 Scratch Register (SCR))
178
Programmable Baud Rate Generator
179
FPGA Register Mapping
179
Table 6-38 Divisor Latch LSB Register (DLL), if DLAB=1
179
Table 6-39 Divisor Latch MSB Register (DLM), if DLAB=1
179
IPMC SPI Register Map
180
LPC I/O Register Map
180
Table 6-40 FPGA Register Map Overview
180
Module Identification Register
182
Serial Redirection Control Register
182
Table 6-41 Module Identification Register
182
Version Register
182
Serial over LAN (SOL) Control Register
183
Table 6-43 Serial Redirection Control Register
183
Table 6-44 Serial over LAN Control Register
183
IPMC Power Level Register
184
Serial Line Routing Register
184
Table 6-45 Serial Line Routing Register
184
Table 6-46 IPMC Power Level Register
184
SPD PROM MUX Control Register
185
Table 6-47 SPD PROM MUX Control Register
185
Reset Registers
186
BIOS Reset Source Register
186
Table 6-48 BIOS Reset Source Register
186
Reset Mask Register
187
Table 6-49 Reset Mask Register
187
BIOS IPMC Watchdog Timeout Register
188
BIOS Push Button Enable Register
188
Table 6-50 BIOS IPMC Watchdog Timeout Register
188
OS Reset Source Register
189
Table 6-51 BIOS Push Button Enable Register
189
Table 6-52 Reset Source Register
189
OS IPMC Watchdog Timeout Register
190
Table 6-53 os IPMC Watchdog Timeout Register
190
IPMC Watchdog Timeout Register
191
Table 6-54 IPMC Watchdog Timeout Register
191
IPMC Reset Source Register
192
Table 6-55 IPMC Reset Source Register
192
RTM SPI Interface Registers
193
Table 6-56 RTM SPI Address/Command Register
193
Table 6-57 RTM SPI Write Register
193
Interrupt Control and Status Registers
194
External Interrupt Status Register
194
RTM Interrupt Status Register
194
Table 6-58 RTM SPI Read Register
194
Table 6-59 External Interrupt Status Register
194
Processor Hot Status/Control Register
195
Table 6-60 Processor Hot Status/Control Register
195
Interrupt Mask and Map Registers
196
Table 6-61 Telecom Status/Control Register
196
Table 6-62 Address Map of Interrupt Mask and Map Registers
196
Telecom Status/Control Register
196
Table 6-63 Interrupt Mask and Map Registers
198
Flash Status and Protection Registers
199
Table 6-64 Flash Status Register
199
Table 6-65 Default Boot SPI Flash Write Enable
200
BIOS Boot Mode Register
201
SFMEM Module Configuration Register
201
Table 6-66 Recovery Boot SPI Flash Write Enable
201
Table 6-67 BIOS Boot Mode Register
201
Table 6-68 SFMEM Module Configuration Register
201
Table 6-69 Update Channel Equalization Control Register
202
Update Channel Equalization Control Register
202
IPMC E-Keying Status Register
203
Table 6-70 IPMC E-Keying Status Register
203
IPMC E-Keying Control Register
204
Table 6-71 IPMC E-Keying Control Register
204
IPMC GPIO Register
205
LED Status and Control Register
205
Table 6-73 LED Status and Control Register
205
NMI Status and Control Register
206
Table 6-74 NMI Status and Control Register
206
Table 6-75 Telecom Backplane Clocking Status Register
207
Table 6-76 Telecom Backplane Clocking Latch Register
207
Table 6-77 Telecom CH1_CLK1A Clock Period MSB Register
207
Telecom Clock Supervision Registers
207
Telecom Clocking Status Registers
207
Table 6-78 Telecom CH1_CLK1A Clock Period LSB Register
208
Table 6-79 Telecom CH1_CLK1B Clock Period MSB Register
208
Table 6-80 Telecom CH1_CLK1B Clock Period LSB Register
208
Telecom Timer Registers
208
Miscellaneous Status/Control Registers
209
Table 6-81 Telecom Timer MSB Register
209
Table 6-82 Telecom Timer LSB Register
209
Table 6-83 CPLD Version and Spare Signal Status Register
209
Scratch Registers
210
Table 6-85 IPMC Scratch Register
210
7 Serial over LAN
211
Overview
211
Installing the Ipmitool
211
SOL Overview
211
Configure SOL Parameters
212
Using Standard IPMI Commands
212
Using Ipmitool
213
Establishing a SOL Session
215
8 Supported IPMI Commands
217
Standard IPMI Commands
217
Global IPMI Commands
217
System Interface Commands
217
Table 8-1 Supported Global IPMI Commands
217
Table 8-2 Supported System Interface Commands
217
Watchdog Commands
218
Table 8-3 Supported Watchdog Commands
218
SEL Device Commands
219
FRU Inventory Commands
219
Table 8-4 Supported SEL Device Commands
219
Table 8-5 Supported FRU Inventory Commands
219
Sensor Device Commands
220
Table 8-6 Supported Sensor Device Commands
220
Chassis Device Commands
221
System Boot Options Commands
221
Table 8-7 Supported Chassis Device Commands
221
Table 8-8 Configurable System Boot Option Parameters
221
Table 8-9 System Boot Options Parameter #96
222
Table 8-10 System Boot Options Parameter #97
223
Table 8-11 System Boot Options Parameter #98
224
Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview
225
Table 8-12 System Boot Options - Parameter #100 - Data Format
226
Table 8-13 System Boot Options Parameter #100 - SET Command Usage
227
Table 8-14 System Boot Options Parameter #100 - GET Command Usage
228
Table 8-15 System Boot Options Parameter #100 - Supported Parameters
229
Table 8-16 Boot_Order Devices
230
LAN Device Commands
231
Table 8-17 Supported LAN Device Commands
231
PICMG 3.0 Commands
232
Table 8-18 Supported PICMG 3.0 Commands
232
Set/Get Power Level
233
Artesyn Specific Commands
234
Serial Output Commands
234
Set Serial Output Command
234
Table 8-19 Serial Output Commands
234
Table 8-20 Request Data of Set Serial Output Command
235
Table 8-21 Response Data of Set Serial Output Command
235
Get Serial Output Command
236
Table 8-22 Request Data of Get Serial Output Command
236
Table 8-23 Response Data of Get Serial Output Command
236
Pigeon Point Specific Commands
237
Table 8-24 Pigeon Point Extension Commands
237
Table 8-25 IPMC Modes
238
Get Status Command
239
Table 8-26 Get Status Command
239
Get Serial Interface Properties Command
241
Table 8-27 Get Serial Interface Properties Command
241
Set Serial Interface Properties Command
242
Table 8-28 Set Serial Interface Properties Command
242
Get Debug Level Command
243
Table 8-29 Get Debug Level Command
243
Set Debug Level Command
244
Table 8-30 Set Debug Level Command
244
Get Hardware Address Command
246
Set Hardware Address Command
246
Table 8-31 Get Hardware Address Command
246
Table 8-32 Set Hardware Address Command
246
Get Handle Switch Command
247
Table 8-33 Get Handle Switch Command
247
Get Payload Communication Time-Out Command
248
Set Handle Switch Command
248
Table 8-34 Set Handle Switch Command
248
Table 8-35 Get Payload Communication Time-Out Command
248
Set Payload Communication Time-Out Command
249
Table 8-36 Set Payload Communication Time-Out Command
249
Disable Payload Control Command
250
Enable Payload Control Command
250
Table 8-37 Enable Payload Control Command
250
Table 8-38 Disable Payload Control Command
250
Hang IPMC Command
251
Reset IPMC Command
251
Table 8-39 Reset IPMC Command
251
Table 8-40 Hang IPMC Command
251
Graceful Reset Command
252
Table 8-41 Graceful Reset Command
252
Get Payload Shutdown Time-Out Command
253
Table 8-42 Get Payload Shutdown Time-Out Command
253
Get Module State Command
254
Set Payload Shutdown Time-Out Command
254
Table 8-43 Set Payload Shutdown Time-Out Command
254
Table 8-44 Get Module State Command
254
Disable Module Site Command
256
Enable Module Site Command
256
Table 8-45 Enable Module Site Command
256
Table 8-46 Disable Module Site Command
256
Reset Carrier SDR Repository Command
257
Table 8-47 Reset Carrier SDR Repository Command
257
9 FRU Information and Sensor Data Records
259
FRU Information
259
Table 9-1 FRU Information
259
MAC Address Record
260
Table 9-2 Artesyn MAC Addresses Record
260
Table 9-3 Artesyn MAC Address Descriptor
261
Table 9-4 Interface Type Assignments
261
E-Keying
262
Table 9-5 Contents of the Blade Point-To-Point Connectivity Record Area
262
Power Configuration
264
Sensor Data Records
264
Table 9-6 Power Configuration
264
Figure 9-1 Location of Temperature Sensors
267
Table 9-8 Sensor Data Records
268
10 Firmware Upgrade
275
HPM.1 Firmware Upgrade
275
Overview
275
Installing the Ipmitool
275
Update Procedure
275
Interface
276
Ipmb-0
276
KCS Interface
276
LAN over Ethernet (BASE)
277
IPMC Upgrade
277
Figure 10-1 IPMC Component Elements
277
BIOS/FPGA Upgrade
278
Figure 10-2 SPI Busses Connection
279
Upgrade Package
280
Table 10-1 HPM Upgrade Package
280
Replacing the Battery
281
Figure A-1 Location of On-Board Battery
281
Related Documentation
285
Artesyn Embedded Technologies - Embedded Computing Documentation
285
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications
285
Manufacturers' Documents
286
Related Specifications
286
Table B-2 Manufacturer's Documents
286
Table B-3 Related Specifications
286
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