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ATCA-7370
Artesyn ATCA-7370 Manuals
Manuals and User Guides for Artesyn ATCA-7370. We have
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Artesyn ATCA-7370 manual available for free PDF download: Installation And Use Manual
Artesyn ATCA-7370 Installation And Use Manual (258 pages)
Brand:
Artesyn
| Category:
Single board computers
| Size: 2 MB
Table of Contents
Table of Contents
3
About this Manual
19
Safety Notes
27
Sicherheitshinweise
33
1 Introduction
39
Features
39
Standard Compliances
40
Table 1-1 Standard Compliances
40
Mechanical Data
41
Mechanical Layout
42
Figure 1-1 Mechanical Layout
42
Mean Time between Failures
43
Ordering Information
43
Table 1-3 Blade Variants - Ordering Information
43
Product Identification
44
Table 1-4 Blade Accessories - Ordering Information
44
2 Hardware Preparation and Installation
45
Unpacking and Inspecting the Blade
45
Environmental and Power Requirements
46
Environmental Requirements
46
Table 2-1 Environmental Requirements
47
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)
48
Power Requirements
49
Table 2-2 Power Requirements
49
Blade Layout
51
Installing the Blade Accessories
52
DIMM Memory Modules
52
Cave Creek Module
54
Figure 2-3 Cave Creek Module
54
Figure 2-4 Cave Creek Module Installation
56
Installing and Removing the Blade
57
Installing the Blade
57
Removing the Blade
59
3 Controls, Indicators, and Connectors
61
Faceplate
61
Faceplate Leds
61
Leds and Interfaces
62
Connectors
64
Faceplate Connectors
64
Table 3-2 RJ45 Console Connector Pinout
64
Table 3-3 USB Connector Pinout
64
Backplane Connectors
65
Table 3-4 Zone 1 Connector P1 Pin Assignment
65
Table 3-5 Zone 2 Connector J20 Pin Assignment
66
Table 3-6 Zone 2 Connector J23 Pin Assignment
66
Table 3-7 Zone 3 Connector J30 Pin Assignment
67
Table 3-8 Zone 3 Connector J31 Pin Assignment
67
Mezzanine Card Connector
68
Table 3-9 Zone 3 Connector J32 Pin Assignment
68
Table 3-10 Mezzanine Card Connector Signals
68
On-Board Connectors
70
Trusted Platform Module (TPM) Header
70
Figure 3-2 TPM Connector Pinout
70
FPGA JTAG Head
71
Switch Settings
71
PCH Switch
71
Figure 3-3 USB 2.0 Flash Disk Module Connector Pinout
71
FPGA Switch
72
Table 3-12 Switch SW1 Setting
72
4 Bios
73
Features
73
Update and Recovery
74
DRAM Support
75
Interrupt Routing
77
PCI Initialization
77
I/O Device Configuration
77
Serial Ports
77
Integrated SATA Controller
77
Boot Options
78
Boot Support for the SAS Controller
78
Network Boot
79
Table 4-1 Network Boot Support Status
79
Console or I/O Redirection
80
Serial over LAN (SOL)
80
IPMI Support
80
Watchdogs
81
SMBIOS Support
81
LED Behavior During POST
81
BIOS Setup Layout
82
Board Information Display
82
USB 2.0 Ports
82
Supported Operating Systems
82
SPI Boot Flash
82
Serial Console and BIOS Printouts
83
BIOS Printouts to DRAM
83
Table 4-2 Printout Floating Structure
83
BIOS Interface Towards os
84
Proprietary BIOS Data Area (BDA) Bytes
84
BIOS CLI Tool - IPMIBPAR
84
Setup Utility
85
Table 4-4 Primary Menu Description
85
Table 4-5 SCT Navigation Keys
86
Main Menu
87
Advanced Menu
88
Boot Configuration
89
Table 4-8 Boot Configuration
89
Processor Configuration
91
Table 4-9 Processor Configuration
91
Peripheral Configuration
92
HDD Configuration
92
Table 4-10 Peripheral Configuration
92
Memory Configuration
93
Table 4-12 Memory Configuration
93
South Bridge Configuration
94
Table 4-13 South Bridge Configuration
94
SMBIOS Event Log
95
Security Menu
96
Boot Menu
97
Save and Exit Menu
98
5 Functional Description
101
Block Diagram
101
Processor
102
Memory
103
DDR3 Main Memory
103
Figure 5-2 Intel Xeon Processor E5-2648L/C604 Chipset Platform
103
Platform Controller Hub (PCH)
104
PCH I/O Controller
104
Figure 5-3 PCH Block Diagram
105
Ethernet Ports
106
ATCA 3.0 Base Interface
106
Fabric Interface ATCA 3.1
106
Faceplate Ethernet Ports
106
Update Channel Ethernet
107
Storage
107
Ipmc
107
Serial Redirection
108
Real Time Clock
108
Serial ATA
109
IPMI over LAN
109
USB 2.0 Interface
109
Smbus Connections
110
Figure 5-4 Overall Smbus Connections
110
Glue Logic FPGA
111
6 Maps and Registers
113
Interrupt Structure
113
Figure 6-1 Interrupt Structure on ATCA-7370
113
Table 6-1 Interrupt Source Signals List
114
PIC (Non-APIC) D31:F0 Interrupt Mapping
115
Table 6-2 Non-APIC (PIC Mode/8259 Mode) Interrupt Mapping
115
APIC (D31:F0) Interrupt Mapping
116
Table 6-3 APIC Mode Interrupt Mapping
116
Non-Maskable Interrupt Generation
118
Registers
120
Table 6-5 Causes of Interrupt
120
Table 6-7 Register Access Type
120
Register Decoding
121
LPC Decoding
121
SPI Register Decoding
122
Table 6-8 LPC I/O Register Map Overview
122
POST Code Register
123
Super IO Configuration Register
123
Table 6-10 POST Code Register
123
Table 6-11 Super I/O Configuration Index Register
123
Table 6-12 Super I/O Configuration Data Register
123
Configuration Mode
124
Entering the Configuration State
124
Exiting the Configuration State
124
Super I/O Configuration Registers
124
Table 6-13 Global Configuration Register Summary
125
Table 6-14 Super IO Logical Device Number Register
125
Table 6-15 Super IO Device Revision Register
125
Table 6-16 Super IO LPC Control Register
126
Table 6-17 Global Super IO SERIRQ and Pre-Divide Control Register
126
Table 6-18 Logical Device Configuration Register
127
Table 6-19 Logical Device Enable Register
127
Table 6-20 Logical Device Base IO Address MSB Register
128
Table 6-21 Logical Device Base IO Address LSB Register
128
Table 6-22 Logical Device Common Decode Ranges
128
Table 6-23 Logical Device Primary Interrupt Register
129
Table 6-24 Logical Device 0X74 Reserved Register
129
UART1 and UART2 Register Map
130
UART Register Overview
130
Table 6-25 Logical Device 0X75 Reserved Register
130
Table 6-26 Logical Device 0Xf0 Reserved Register
130
Table 6-27 UART Register Overview
130
UART Registers DLAB=0
131
Receiver Buffer Register (RBR)
131
Table 6-28 Receiver Buffer Register (RBR) if DLAB=0
131
Transmitter Holding Register (THR)
132
Interrupt Enable Register (IER)
132
Table 6-29 Transmitter Holding Register (THR) if DLAB=0
132
Table 6-30 Interrupt Enable Register (IER) if DLAB=0
132
Interrupt Identification Register (IIR)
133
Table 6-31 UART Interrupt Priorities
133
Table 6-32 Interrupt Identification Register (IIR)
133
Table 6-33 Interrupt Identification Register Decode
134
FIFO Control Register (FCR)
135
Table 6-34 FIFO Control Register (FCR)
135
Line Control Register (LCR)
136
Table 6-35 Line Control Register (LCR)
136
Modem Control Register (MCR)
138
Table 6-36 Modem Control Register (MCR)
138
Line Status Register (LSR)
139
Table 6-37 Line Status Register (LSR)
140
Modem Status Register (MSR)
144
Table 6-38 Modem Status Register (MSR)
144
Scratch Register (SCR)
146
Programmable Baud Rate Generator
146
Table 6-39 Scratch Register (SCR)
146
FPGA Register Mapping
147
LPC I/O Register Map
147
Table 6-40 Divisor Latch LSB Register (DLL), if DLAB=1
147
Table 6-41 Divisor Latch MSB Register (DLM), if DLAB=1
147
IPMC SPI Register Map
148
Module Identification Register
150
Table 6-43 Module Identification Register
150
Version Register
151
Serial Redirection Console Register
151
Table 6-45 Serial Redirection Control Register
151
SOL Control Register
152
Serial Routing Register
152
Table 6-46 SOL Control Register
152
Table 6-47 Serial Routing Register
152
IPMC Power Level Register
153
Table 6-48 IPMC Power Level Register
153
Payload Power Control Register
154
I2C Switch Control Register
154
Table 6-49 Payload Power Control Register
154
Table 6-50 I2C Switch Control Register
154
Payload Power-Button Register
155
Reset Registers
155
Reset Mask Register
155
Table 6-51 Payload Power-Button Register
155
Reset Function Register
156
Table 6-53 Reset Function Register
156
IPMC Reset Payload Request Register
157
Table 6-54 IPMC Reset Payload Request Register
157
BIOS Reset Payload Request Register
158
OS Reset Payload Request Register
158
Table 6-55 BIOS Reset Payload Request Register
158
Table 6-56 os Reset Payload Request Register
158
Payload Reset Source for IPMC Register
159
Payload Reset Source for BIOS Register
159
Table 6-57 Payload Reset Source for IPMC Register
159
Payload Reset Source for os Register
160
Table 6-58 Payload Reset Source for BIOS Register
160
Table 6-59 Payload Reset Source for os Register
161
IPMC Watchdog Timeout Register
162
10IPMC Watchdog Timeout for BIOS Register
162
Table 6-60 IPMC Watchdog Timeout Register
162
Table 6-61 IPMC Watchdog Timeout for BIOS Register
162
11IPMC Watchdog Timeout for os Register
163
12FPGA-Payload-Watchdog Threshold Register
163
Table 6-62 IPMC Watchdog Timeout for os Register
163
Table 6-63 FPGA-Payload-Watchdog Threshold Low-Byte Register
163
13FPGA Payload Watchdog Clear Register
164
14FPGA-IPMC-Watchdog Threshold Register
164
Table 6-64 FPGA-Payload-Watchdog Threshold Low-Byte Register
164
Table 6-65 FPGA-Payload-Watchdog Clear Register
164
Table 6-66 FPGA-IPMC-Watchdog Threshold Register
164
Flash Control Register
165
RTM Status and Control Register
165
Table 6-67 Flash Control Register
165
Table 6-68 RTM Status and Control Register
165
Blue LED Status and Control Register
166
Table 6-69 Blue LED Status and Control Register
166
User LED Status and Control Register
167
Table 6-70 User LED Status and Control Register
167
Miscellaneous Status and Control Register
168
Debug Switch and LED Status Register
168
Table 6-71 Miscellaneous Status and Control Register
168
Table 6-72 Debug Switch and LED Status Register
168
Scratch Register
169
POST Code Register
169
Standard Status Codes
169
Table 6-73 LPC Scratch Registers
169
Table 6-74 POST Code Register
169
Table 6-75 Component Status Codes
169
Table 6-76 Progress Status Codes
172
Table 6-77 Architectural Status Codes
173
7 Serial over LAN
175
Overview
175
Installing the Ipmitool
175
Configuring SOL Parameters
176
Using Standard IPMI Commands
176
Using Ipmitool
177
Establishing a SOL Session
179
8 Supported IPMI Commands
181
Standard IPMI Commands
181
Global IPMI Commands
181
System Interface Commands
181
Table 8-1 Supported Global IPMI Commands
181
Table 8-2 Supported System Interface Commands
181
BMC Watchdog Commands
182
Table 8-3 Supported Watchdog Commands
182
SEL Device Commands
183
FRU Inventory Commands
183
Table 8-4 Supported SEL Device Commands
183
Table 8-5 Supported FRU Inventory Commands
183
Sensor Device Commands
184
Chassis Device Commands
184
Table 8-6 Supported Sensor Device Commands
184
Table 8-7 Supported Chassis Device Commands
184
System Boot Options Commands
185
Table 8-8 Configurable System Boot Option Parameters
185
Table 8-9 System Boot Options Parameter #96
186
Table 8-10 System Boot Options Parameter #97
187
Table 8-11 System Boot Options Parameter #98
188
Figure 8-1 System Boot Options Parameter #100 - Information Flow
189
Table 8-12 System Boot Options - Parameter #100 - Data Format
190
Table 8-13 System Boot Options Parameter #100 - SET Command Usage
190
Table 8-14 System Boot Options Parameter #100 - GET Command Usage
191
Table 8-15 System Boot Options Parameter #100 - Supported Parameters
193
Table 8-16 Boot_Order Devices
194
Event Commands
195
LAN Device Commands
195
Table 8-17 Supported Event Commands
195
Table 8-18 Supported LAN Device Commands
195
PICMG 3.0 Commands
196
Table 8-19 Supported PICMG 3.0 Commands
196
Artesyn Embedded Technologies Specific Commands
198
Set/Get Feature Configuration Commands
198
Table 8-20 Set/Get Feature Configuration Commands
198
Get Feature Configuration Command
199
Set Feature Configuration Command
199
Table 8-21 Set Feature Configuration Command
199
Table 8-22 Get Feature Configuration Command
199
Serial Output Commands
200
Table 8-23 Feature Selector Assignments
200
Table 8-24 Serial Output Commands
200
Get Serial Output Command
201
Set Serial Output Command
201
Table 8-25 Set Serial Output Command
201
OEM Set/Get ACPI Power Commands
202
Table 8-26 Get Serial Output Command
202
Table 8-27 OME Set/Get ACPI Power Commands
202
OEM Get ACPI Power State (0X18)
203
OEM Set ACPI Power State (0X17)
203
Table 8-28 OEM Set ACPI Power State Command
203
OEM Set/Get Performance Commands
204
Table 8-29 OEM Get ACPI Power State Command
204
Table 8-30 OEM Set/Get Performance Commands
204
OEM Set Performance Mode (0X21)
205
Table 8-31 OEM Set Performance Mode Command
205
OEM Get Performance Mode (0X22)
206
Table 8-32 OEM Get Performance Mode Command
206
Pigeon Point Specific Commands
207
Table 8-33 Pigeon Point Extension Commands
207
Get Status Command
208
Table 8-35 Get Status Command
208
Get Serial Interface Properties Command
211
Table 8-36 Get Serial Interface Properties Command
211
Set Serial Interface Properties Command
212
Table 8-37 Set Serial Interface Properties Command
212
Get Debug Level Command
213
Table 8-38 Get Debug Level Command
213
Set Debug Level Command
214
Table 8-39 Set Debug Level Command
214
Get Hardware Address Command
215
Set Hardware Address Command
215
Table 8-40 Get Hardware Address Command
215
Table 8-41 Set Hardware Address Command
215
Get Handle Switch Command
216
Table 8-42 Get Handle Switch Command
216
Get Payload Communication Time-Out Command
217
Set Handle Switch Command
217
Table 8-43 Set Handle Switch Command
217
Table 8-44 Get Payload Communication Time-Out Command
217
Set Payload Communication Time-Out Command
218
Table 8-45 Set Payload Communication Time-Out Command
218
Disable Payload Control Command
219
Enable Payload Control Command
219
Table 8-46 Enable Payload Control Command
219
Table 8-47 Disable Payload Control Command
219
Hang IPMC Command
220
Reset IPMC Command
220
Table 8-48 Reset IPMC Command
220
Table 8-49 Hang IPMC Command
220
Graceful Reset Command
221
Table 8-50 Graceful Reset Command
221
Get Payload Shutdown Time-Out Command
222
Table 8-51 Get Payload Shutdown Time-Out Command
222
Get Module State Command
223
Set Payload Shutdown Time-Out Command
223
Table 8-52 Set Payload Shutdown Time-Out Command
223
Table 8-53 Get Module State Command
223
Disable Module Site Command
225
Enable Module Site Command
225
Table 8-54 Enable Module Site Command
225
Table 8-55 Disable Module Site Command
225
Reset Carrier SDR Repository Command
226
Table 8-56 Reset Carrier SDR Repository Command
226
9 FRU Information and Sensor Data Records
227
FRU Information
227
Power Configuration
228
Table 9-2 Power Configuration
228
Figure 9-1 ATCA-7370 Temperature Sensors
229
Figure 9-2 ATCA-7370-S Temperature Sensors
230
Sensor Data Records
231
Table 9-3 Sensor Data Records
231
10 Firmware Upgrade
243
HPM.1 Firmware Upgrade
243
Overview
243
Installing the Ipmitool
243
Update Procedure
243
Interface
244
KCS Interface
244
Ipmb-0
244
IPMI over LAN (BASE)
244
IPMC Upgrade
245
Figure 10-1 IPMC Component Elements
245
BIOS/FPGA Update
246
Figure 10-2 SPI Busses Connection
247
Upgrade Package
248
Table 10-1 HPM Upgrade Package
248
Replacing the Battery
249
Figure A-1 Location of On-Board Battery
250
Troubleshooting
253
Error List
253
CPU Blade Is Not Functioning Properly
253
B.1 Error List
253
Related Documentation
255
Artesyn Embedded Technologies - Embedded Computing Documentation
255
Related Specifications
255
Table C-1 Artesyn Embedded Technologies - Embedded Computing Publications
255
Table C-2 Related Specifications
255
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