ARM GP4020 GPS Receiver Processor Manuals

Manuals and User Guides for ARM GP4020 GPS Receiver Processor. We have 1 ARM GP4020 GPS Receiver Processor manual available for free PDF download: Design Manual

ARM GP4020 Design Manual

ARM GP4020 Design Manual (215 pages)

GPS Baseband Processor

Brand: ARM | Category: GPS | Size: 2 MB

Table of Contents

Manual Revision History
2
Table of Contents
3
Trademarks
5
Document References
6
Document Conventions
6
1 Introduction

7
- GP4020 GPS Baseband Processor Overview
  7
- Features
  7
- Functional Description
  8
- Internal SRAM
  11
- Typical Application
  14
2 Gp4020 Package and Electrical Connections

17
3 Arm7Tdmi Microprocessor

25
- ARM7TDMI Instruction Set Architecture
  25
- The Thumb Concept
  25
- Thumb's Advantages
  25
- Operating Modes
  28
- Register Sets
  29
- Low Power ARM7TDMI Sleep Mode
  30
4 Boot Rom

33
- Functional Description
  33
- UART Download Data Protocol
  34
5 The Bµild BUS

37
- Bus Masters
  37
- Bus Slaves
  37
- Bus Signals
  38
6 Bµild SERIAL INPUT OUTPUT (BSIO) INTERFACE

39
- Overview
  39
- Operational Description
  40
- BSIO Frequency Divider
  45
- Operation
  45
- BSIO Slave Select Logic
  46
- BSIO Interrupt Control
  47
- BSIO Write Buffer and Control Register
  47
- BSIO Read Buffer
  48
- BSIO Sequencer
  48
- BSIO Registers
  50
- All Others
  50
12 Channel Correlator (Corr)

55
- Introduction
  55
  - Clock Generator
    55
  - Timebase Generator
    55
  - Status Registers
    57
  - Address Decoder
    57
  - Bus Interface
    57
  - UIM Interface
    58
- Tracking Modules
  58
- Software Requirements
  61
- Signal Tracking
  64
- Controlling the 12 Channel Correlator
  65
  - Search Operation
    65
  - Preset Mode
    67
- Channel Correlator Interface Timing
  69
- 12-Channel Correlator Register Maps
  70
  - RESET_CONTROL Register
    89
  - Status Register
    91
8 Dma Controller (Dmac)

97
- Single-Addressed (Fly-By) Data Transfers
  97
- Dual-Addressed (Buffered) Data Transfers
  103
- DMAC Triggering
  105
- Cautionary Notes
  107
9 General Purpose Input Output (Gpio) Interface

109
- Introduction
  109
- Write Cycle
  110
- Initialisation
  111
- GPIO Registers
  111
10 Interrupt Controller (Intc)

113
11 Memory Peripheral Controller (Mpc)

115
- Introduction
  115
- GP4020 Memory Area 1 Configuration
  115
- GP4020 Memory Area 2 Configuration
  116
- GP4020 Memory Area 3 Configuration
  117
- GP4020 Memory Area 4 Configuration
  118
12 Peripheral Control Logic (Pcl)

119
- Introduction
  119
- Chip Reset Logic
  119
- PLL Enable Logic
  124
- Multiplex Logic
  125
- Interrupt and Wake-Up Logic
  127
- Chip-Wide Power Control Modes
  129
- Peripheral Control Logic Registers
  130
- Test Mode
  134
13 Real Time Clock (Rtc)

137
- Introduction
  137
- 32Khz Crystal Oscillator
  137
- Real Time Clock Registers
  138
14 System Clock Generator (Scg)

141
- Introduction
  141
- 40Mhz Low Level Differential Input
  142
- Processor Crystal Oscillator
  143
- Phase Locked Loop (PLL)
  145
- System Clock Generator Power Consumption Issues
  151
- System Clock Generator Registers
  152
1 Pps Timemark Generator

155
16 Up-Integration Module (Uim)

173
17 Universal Asynchronous Receiver Transmitter (Uart)

175
- Introduction
  175
- Baud Rate Generation
  175
- Connections to the Bµild Bus and the Firefly MF1 Core
  180
18 Watchdog Timer (Wdog)

182
- Design Features
  182
- Operational Description
  183
- Start-Up Behaviour
  183
- Watchdog Register Map
  184
19 Address Maps

187
- GP4020 System Address Map
  187
  - Address Range
    187
  - System Address Map
    189
- GP4020 Firefly MF1 Address Map
  189
20 Input / Output Pin Characteristics

191
- Pin Types
  191
- Input Delays
  193
- Tolerant Inputs
  194
- Output Delays
  194
- Cell DC Characteristics
  196
21 Timing Characteristics

199
Indexes

205

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