ViewSonic VX500PLUS-1 Service Manual page 36

15” color tft lcd display
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The gm5010 has an Input Format Measurement block (the IFM) providing the capability
of measuring the horizontal and vertical timing parameters of the input video source. This
information may be used to determine the video format and to detect a change in the input
format. It is also capable of detecting the field type of interlaced formats.
The IFM features a host programmable reset, separate from the regular gm5010 soft reset.
This reset disables the IFM, reducing power consumption. The IFM is capable of
operating while gm5010 is running in power down mode.
Horizontal measurements are measured in terms of the selected IFM_CLK (either T_CLK
or R_CLK/4), while vertical measurements are measured in terms of HSYNC pulses.
The gm5010 OSD controller supports both character-mapped and bitmapped modes. A
user programmable palette of 256 true colors (255 colors, + 1 transparent) is available. In
character mapped mode, a maximum of four colors per character are available. In 8-bit
bitmapped mode, any pixel can be assigned any one of 256 user-defined true colors. In 4-bit
bitmapped mode, any pixel can be assigned any one of 16 user-defined true colors (15 colors
plus one transparent).
The gm5010 incorporates an embedded microprocessor, or OCM (On-Chip
Microprocessor). This processor is intended to simplify the gm5010 system software
implementation by providing embedded macro functions such as OSD menu configurations. It
is not intended to replace the system microprocessor.
An arbitration mechanism handles the register access requests from the OCM and the
system. micro.
4. DDC 2 B
ICM6 & ICM7 (24LC21A) can continuously transmit its extended identification, "EDID" using
DDC1 communication channel. In addition, the monitor can respond to a request for EDID, or
complete VDIF, to be transmitted using DDC2, level B commands. Pin6 SCL is clock input for
DDC 2B, pin5 SDA for data input, and pin7 VCLK is clock input for DDC1.
In DDC1 data transfer (UNI-directional mode), the VCLK input pin is used as an input
clock for data transmission and SDA output pin is used as serial data line the SCL pin will
hold high. The DDC2B node (BI-directional mode) BUS consists of two wires. SCL is for
the data transmission clock and SDA is for the data line.
ViewSonic Corporation
33
Confidential – Do Not Copy
VX500+-1

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