Cpu Configuration; Hardware Prefetcher; Adjacent Cache Line Prefetch; Max Cpuid Value Limit - DFI CA900-B User Manual

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3
BIOS Setup

CPU Configuration

This section is used to configure the CPU. It will also display the detected CPU
information.
Configure advanced CPU settings
Module Version:3F.15
Manufacturer
Celeron(R) Dual-Core CPU
Frequency
FSB Speed
Cache L1
Cache L2
Ratio Actual Value:9.5
Hardware Prefecher

Adjacent Cache Line Prefetch

Max CPUID Value Limit

Execute-Disable Bit Capability
Core Multi-Processing
Intel (R) Speedstep (tm) Tech

Hardware Prefetcher

Enables or disables the Hardware Prefetcher feature.
Adjacent Cache Line Prefetch
Enables or disables the Adjacent Cache Line Prefetch feature.
Max CPUID Value Limit
Set this field to Disabled when using Windows XP. Set this field to Enabled
when using legacy operating systems so that the system will boot even when
it doesn't support CPUs with extended CPUID function.
Execute Disable Bit Capability
When this field is set to Disabled, it will force the XD feature flag to always
return to 0.
Core Multi-processing
When this field is set to Disabled, it disables one execution core of each CPU
die.
Intel (R) SpeedStep(TM) Tech
Enables or disables GV3.
40
BIOS SETUP UTILITY
Advanced
: Intel
T3100 @ 1.90GHz
: 1.90GHz
: 800MHz
: 64KB
: 1024KB
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[Enabled]
[Enabled]
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
For UP platforms,
leave it enabled.
For DP/MP servers,
it may use to tune
performance to the
specific application.
Select Screen
← →
Select Item
↑↓
+ -
Change Option
F1
General Help
F10
Save and Exit
ESC
Exit

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