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2.2 CCD (ICX220AK/ICX221BK)
This IC functions as an interline CCD (Charge
Coupled Device = one of solid-state pickup
devices). Since this CCD conforms to the SD
mode of the DV standard, it has an optimum
number of vertical pixels for the MPEG2 main level
and it realizes a horizontal resolution of 450 TV
lines. As same as general CCD's currently in use,
this CCD is capable of camera shaking correction
and electronic panning and tilting owing to the
extension area of 33 percent extra in both the
vertical and horizontal directions.
Moreover, this CCD provides high quality wide
picture whose aspect ratio is exactly 16:9 without
vertical interpolation.
High sensitivity and low dark current are realized
thanks to adoption of the Super HAD CCD
technology with the color filters of yellow, cyan,
magenta and complementary green mosaic filters.
This CCD has an electronic shutter function that is
able to vary charge storage time by the field period
read system.
Frame period read system is realized by joint use
of the newly developed TG IC.
ELEMENT STRUCTURE
Optical size
Total pixels
Effective pixels
4:3 NTSC
16:9 18MHZ
16:9 5fsc
OB
Board material
Pin No.
Label
In/Out
V φ 4
1
In
V φ 3
2
In
V φ 2
3
In
V φ 1
4
In
5
GND
6
TEST
7
VDD
1/4 inch size format
NTSC: 998 (H) × 677 (V) approx. 680,000 pixels, PAL: 998×797 approx. 800,000 pixels
NTSC: 962 (H) × 654 (V) approx. 630,000 pixels, PAL: 962×774 approx. 740,000 pixels
NTSC: 711 (H) × 485 (V) approx. 340,000 pixels, PAL: 702×575 approx. 400,000 pixels
NTSC: 948 (H) × 485 (V) approx. 460,000 pixels, PAL: 936×575 approx. 540,000 pixels
NTSC: 942 (H) × 485 (V) approx. 460,000 pixels, PAL: 922×575 approx. 530,000 pixels
H direction: Front 4 pixels, Rear 32 pixels
V direction: Front 11pixels, Rear 12 pixels
Silicon
Table 2-2-1 CCD functions
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
-
Ground
-
Open
-
Power supply
Table 2-2-2 CCD pin function
7
6
5
C y
M g
C y
G
C y
M g
8
9
10
Fig. 2-2-1 CCD block diagram
Interline type CCD image sensor
Pin No.
Label
In/Out
8
VOUT
9
GND
φ RG
10
H φ 1
11
H φ 2
12
φ SUB
13
14
VL
2-2
4
3
2
Ye
C y
Ye
G
M g
G
Ye
C y
Ye
M g
G
M g
Ye
C y
Ye
∗
G
M g
G
Horizontal-Register
11
12
13
Description
Out
Video signal output
-
Ground
In
Reset gate clock
In
Horizontal register transfer clock
In
Horizontal register transfer clock
In
Substrate clock
-
Protect transistor bias
1
Photo
∗
Sensor
14
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