Lsi Pin Description （Lsi端子機能表 - Yamaha SP2060 Service Manual

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LSI PIN DESCRIPTION （LSI端子機能表）
CONTENTS （目次）
• AK4393-VF-E2 (XW029A00) DAC (Digital to Analog Converter) ......... 17
• AK5385BVF-E2 (X5364B00) ADC (Analog to Digital Converter) ......... 17
• HD6417727F160CV (X2890B00) CPU (Microprocessor 32 bit) ............ 18
• YSS919B-HZ (XZ693B00) DSP7 (Digital Signal Processor) ................. 20
• KSZ872ISL (X5621A00) PHYceiver ........................................................ 22
• LC4032V-75TN48C (X7109A00)
• AK4393-VF-E2 (XW029A00) DAC (Digital to Analog Converter)
Pin
Name I/O
no.
1 DVSS - Digital Ground Pin
2 DVDD - Digital Power Supply Pin, 3.3V or 5.0V
3 MCLK I Master Clock Input Pin
4 PD I Power-Down Mode Pin
When at "L",the Ak4393 is in power-down mode and
is held in reset.
The AK4393 should always be reset upon power-
up.
5 BICK I Audio Serial Data Clock Pin
The clock of 64fs or more than is recommended to
be input on this pin.
6 SDATA I Audio Serial Data Input Pin
2's complement MSB-first data is input on this pin.
7 LRCK I L/R Clock Pin
8 SMUTE I Soft Mute Pin
When this pin goes "H", soft mute cycle is initiated.
When returning "L",the output mute releases.
CS I Chip Select Pin in serial mode
9 DFS I Doubla speed sampling mode Pin (Internal pull-down
pin)
"L": Normal Speed, "H": Double Speed
10 DEM0 I De-emphasis Enable pin
CCLK I Control Data Clock Pin in serial mode
11 DEM1 I De-emphasis Enable pin
CDTI I Control Data Input Pin in serial mode
12 DIF0 I


13 DIF1 I Digital Input Format Pin

14 DIF2 I
• AK5385BVF-E2 (X5364B00) ADC (Analog to Digital Converter)
Pin
Name I/O
no.
1 VREFL I Lch voltage reference input
2 AVSS - Analog ground
3 VCOM O Common voltage output
4 LIN+ I Lch analog positive input
5 LIN- I Lch analog negative input
6 CKS0 I Master clock select 0
7 DVDD - Digital power supply
8 DVSS - Digital ground
9 OVF O Analog input overflow detect
10 PDN I Power down mode
11 DIF I Audio interface format
12 M/S I Master / Slave mode
13 LRCK I/O Output channel clock
14 BICK I/O Audio serial data clock
CPLD (Complex Programmable Logic Device) .................................. 22
Function
Function
Pin
Name I/O
no.
15 BVSS I Substrate Ground Pin, 0V
16 VREFL I Low Level Voltage Reference Input Pin
17 VREFH - High Level Voltage Reference Input Pin
18 AVDD - Analog Power Supply Pin, 5V
19 AVSS O Analog Ground Pin, 0V
20 AOUTR- O Rch Negative analog output Pin
21 AOUTR+ O Rch Positive analog output Pin
22 AOUTL- O Lch Negative analog output Pin
23 AOUTL+ O Lch Positive analog output Pin
24 VCOM O Common Voltage Output Pin, 2.6V
Parallel/Serial Select Pin (Internal pull-up pin)
25 P/S I "L": Serial control mode, "H": Parallel control mode
26 CKS0 I


27 CKS1 I Master Clock Select Pin

28 CKS2 I
Pin
Name I/O
no.
15 SDTO O Audio serial date output
16 CKS1 I Master clock select
17 MCLK I Master clock input
18 DFS0 I Sampling speed select 0
19 HPFE I High pass filter enable
Sampling speed select 1
20 DFS1 I
21 BVSS - Substrate ground
22 AVSS - Analog ground
Analog power supply
23 AVDD -
24 RIN- I Rch analog negative input
25 RIN+ I Rch analog positive input
26 TEST I Test pin
27 AVSS - Analog ground
28 VREFR I Rch voltage reference input
SP2060
ANA: IC101, 201, 301
Function
ANA: IC501
Function
17