Sony ICD-55 Service Manual page 11

Pin No. Pin Name
74 XBCK
75 RTCDI
76 RTCDO
77 RTCCLK
78 IC
79 X2
80 X1
81 VDD1
82 XT1
83 XT2
84 XRESET
85 SYNCIN
86 WAKEUP
87 RTCINT
88 —
89 LPMODE
90 AVREFO
91 to 98 FMIO0 to FMIO7
99 AVSS
100 BATT
I/O
O DSP bit clock signal output to the MSM7590L (IC101)
I
Serial data input from the RS5C348A (IC703)
O
Serial data and DSP register control data output to the RS5C348A (IC703)
O
Serial data and DSP register control data transfer clock signal output to the RS5C348A (IC703)
—
Fixed at "L"
O
Main system clock output terminal (5 MHz)
I
Main system clock input terminal (5 MHz)
— Power supply terminal (+3.3V)
I
Sub system clock input terminal (32.768 kHz)
O
Sub system clock output terminal (32.768 kHz) Not used (open)
System reset signal input from the reset signal generator (IC505) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
I
Interrupt input terminal of the DSP X (R) sync
I Key interruption processing start signal input terminal
I
Interrupt input from the RS5C348A (IC703) (2 Hz)
O
Not used (open)
O
Filter selection signal output terminal "L": SP mode, "H": LP mode
O
Reference voltage output terminal (for A/D converter)
I/O
Two-way data bus with the flash memory (IC702) (bit 0 to bit 7)
—
Ground terminal (for A/D converter)
I
Dry battery voltage detection signal input terminal (A/D input)
Function
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