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CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
System BIOS Cacheable
Video RAM Cacheable
Memory Hole At 15M-16M
AGP Aperture Size (MB)
SDRAM ECC Setting
Super Bypass Mode
SDRAM Timing setting by
SDRAM PH Limit
SDRAM Idle Limit
SDRAM Trc Timing Value
SDRAM Trp Timing Value
SDRAM Tras Timing Value
SDRAM CAS Latency
SDRAM Trcd Timing Value
↑↓→← Move
Enter:Select
F5:Previous Values
Advanced Chipset Features
Enabled
Enabled
Disabled
128
Disabled
Disabled
Manual
32 Cycle
8 Cycle
4 Cycle
2 Cycle
2 Cycle
2 Cycle
2 Cycle
+/-/PU/PD:Value
F10:Save
F6:Fail-Safe Defaults
Item Help
Menu Level
ESC:Exit
F1:General Help
F7:Optimized Defaults
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