Aiwa XR-MP50 Service Manual page 44

IC, MAS3507D-G10
Pin No. Pin Name
1 TE
2 POR
3 I2CC
4 I2CD
5 VDD
6 VSS
7 DCEN
8 EOD
9 RTR
10 RTW
11 DCSG
12 DCSO
13 VSENS
14 PR
15 PCS
16 PI19
17 PI18
18 PI17
19 PI16
20 PI15
21 PI14
22 PI13
23 PI12
24 SOD
25 SOI
26 SOC
I/O
I Test Enable. (Connected to VSS)
I Reset, active low.
2
I/O I C clock line.
2
I/O I C data line.
– Positive supply for digital parts.
– Ground supply for digital parts.
I Enable DC/DC converter.
O PIO end of DMA, active low.
O PIO ready to read, active low.
O PIO ready to write, active low. (Not used)
– DC converter transistor ground. (Connected to VSS)
O DC converter transistor open drain. (Connected to VSS)
I DC converter voltage sense. (Connected to VDD)
I PIO-DMA request or read/write.
I PIO chip select, actove low. (Connected to VSS)
PIO Data [19]
I/O 1. Demand pin in SDI mode.
2. data bit [7], MSB (PIO-DMA input mode)
PIO Data [18]
I/O 1. MPEG header bit 11-MPEG ID (SDI mode).
2. data bit [6] (PIO-DMA input mode).
PIO Data [17]
I/O 1. MPEG header bit 12-MPEG ID (SDI mode).
2. data bit [5] (PIO-DMA input mode).
PIO Data [16]
I/O 1. SIC*, alternative input for SIC (SDI mode).
2. data bit [4] (PIO-DMA input mode).
PIO Data [15]
I/O 1. SII*, alternative input for SII (SDI mode).
2. data bit [3] (PIO-DMA input mode).
PIO Data [14]
I/O 1. SID*, alternative input for SID (SDI mode)
2. data bit [2] (PIO-DMA input mode).
PIO Data [13]
I/O 1. MPEG header bit 13-Layer ID (SDI ,mode)
2. data bit [1] (PIO-DMA input mode).
PIO Data [12]
I/O 1. MPEG header bit 14-Layer ID (SDI ,mode)
2. data bit [0] (PIO-DMA input mode).
O Serial output data.
O Serial output frame identification.
O Serial output clock.
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Description