Pcie Interface; Ethernet Phys - Digilent NetFPGA-1G-CML Reference Manual

NetFPGA-1G-CML™ Board Reference Manual
available in the Xilinx 7-Series FPGAs Configuration User Guide (UG470) and application note XAPP587 BPI Fast
Flash Memory data sheet for more specifics regarding device operation.
8 SD Card
The NetFPGA-1G SD card connector supports a second non-volatile storage resource which is also removable. This
connector supports a standard size SD memory card and meets all physical layer requirements of both SPI and SD
bus protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at
3.3V to support SC, HC, and XC class SD cards. Please see SD Specifications Part 1 Physical Layer Simplified
Specification by the Technical Committee of the SD Card Association for more details regarding the use of SD
memory cards with this connector.
9

PCIe Interface

The NetFPGA-1G is designed with a PCI-Express form factor to support interconnection with common processor
motherboards. Four of the FPGA's eight high speed serial GTX transceivers are dedicated to implementing up to
four-lanes of Gen. 2.0 (5 GB/s) PCIe communications with a host processing system. These transceivers work in
conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a
scalable, high performance PCI Express I/O core.
This core is configured and incorporated into designs using either the Xilinx ISE Coregen tool or via instantiation
and customization from the Vivado Design Suite IP catalog. Please refer to the Xilinx 7 Series FPGAs Integrated
Block for PCI Express V2.0 (PG054) product guide and 7 Series FPGAs GTX/GTH Transceivers (UG476) user guide for
more information.

10 Ethernet PHYs

Four Realtek RTL8211 Ethernet transceivers (PHYs) are provided to interface to network connections via on-board
RJ-45 connectors. Each RJ-45 has two LEDs to indicate link status and activity. Each PHY controls three LEDs: two
on an associated RJ-45 and a third on-board (LD5-LD8). The Phys are programmed via a shared MDIO bus and are
accessed via MDIO addresses 1 through 4: corresponding to connectors ETH1 through ETH4 on the PCB. At reset,
each PHY defaults to 1Gbps with the LED configuration shown in Table 2.
On each RJ45, the bottom LED is the one that is closest to the PCIe connector. The default behavior of the on-
board LED is to mimic that of the top RJ45 LED. The default auto-negotiation behavior allows each PHY to
independently adjust its rate to 10/100 Mbps or 1Gbps as needed.
Data is transferred to and from the PHYs via a Reduced Gigabit Media Independent Interface (RGMII). This is
similar to the Gigabit Media Independent Interface (GMII), which uses eight bits for both transmit and receive
data. RGMII achieves the same data rate with half the number of data bits and double-data-rate clocking. 1 Gbps
data transfers are thereby achieved using a 125MHz clock with four bits transferred on each clock edge for both
send and receive. This provides a significant reduction in the number of FPGA I/O pins required to support the four
Ethernet interfaces.
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