Oscillators And Clocks - Digilent NetFPGA-1G-CML Reference Manual

Versatile, low-cost network hardware development platform
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NetFPGA-1G-CML™ Board Reference Manual
The Xilinx Kintex-7 Data Sheet: DC and AC Switching Characteristics (DS182) provides more information on the
power supply requirements of the FPGA board.
Supply
Derived From
5.0 V
12.0 V
3.3 V
12.0 V
2.0 V
5.0 V
1.8 V
12.0 V
1.8 V
3.3 V
1.5 V
12.0 V
1.2 V
12.0 V
1.0 V
12.0 V
1.0 V
3.3 V
0.9 V
3.3 V
0.75 V
3.3 V
VADJ
12.0 V
3

Oscillators and Clocks

On-board oscillators support various board subsystems. A low-jitter 125 MHz oscillator is provided for the Ethernet
PHYs and a 50 MHz oscillator drives the FPGA master configuration clock. The Cypress FX2LF and Microchip PIC
microcontroller each contain on-chip oscillators running at 24 MHz and 8 MHz, respectively.
The main FPGA system clock is provided by an ultra-low-jitter 200 MHz differential oscillator connected to pins
AA2 and AA3 in I/O bank 34. This can drive up to ten internal PLLs (Phase Locked Loops) and MMCMs (Mixed-
Mode Clock Managers) on the FPGA for high-performance multi-clock-domain designs. Please refer to the Xilinx 7-
Series Clock Resources User Guide (UG472) for more details on FPGA internal clocking resources.
4
FPGA Memory
The XC7K325T FPGA includes 445 on-chip Block RAMs (BRAMs) of 36Kb, or 4096 bytes with two-bit error
correction, which amounts to a total of 1.78 MB of on-chip, error-corrected static RAM that can be used for a
variety of purposes ranging from program storage for deeply embedded "bare metal" applications to data
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
USB HID; FMC
SD Card; Ethernet PHYs; Cypress FX2LP; Microchip PIC; BPI
Flash; FPGA I/O Banks 14,15; FMC; PMODs
FPGA auxiliary supply, VCC
backup.
QDRII+ supply
FPGA GTX transceiver Quad PLL
DDR3; FPGA I/O Bank 34
FPGA GTX transceiver termination
FPGA GTX analog supply
FPGA Core
QDRII+ reference
DDR3 reference
FPGA I/O Banks 12, 13; FMC; Configurable.
SET_VADJ2
SET_VADJ1
FPGA AF20
FPGA AF19
0
0
0
1
1
0
1
1
Table 1. On-board power supplies.
Application
; Backup battery; Real-time clock
BAT
VADJ
1.2 V
1.8 V
2.5 V
3.3 V
Page 4 of 21

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