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NetFPGA-1G-CML™ Board Reference Manual
Revised July 16, 2014
This manual applies to the NetFPGA-1G-CML rev. E
Overview
The NetFPGA-1G-CML is a versatile, low-cost network hardware development platform featuring a Xilinx® Kintex®-
7 XC7K325T FPGA and includes four Ethernet interfaces capable of negotiating up to 1 GB/s connections. 512 MB
of 800 MHz DDR3 can support high-throughput packet buffering while 4.5 MB of QDRII+ can maintain low-latency
access to high demand data, like routing tables. Rapid boot configuration is supported by a 128 MB BPI Flash,
which is also available for non-volatile storage applications. The standard PCIe form factor supports high speed x4
Gen 2 interfacing. The FMC carrier connector provides a convenient expansion interface for extending card
functionality via Select I/O and GTX serial interfaces. The FMC connector can support SATA-II data rates for
network storage applications. The FMC connector can also be used to extend functionality via a wide variety of
other cards designed for communication, measurement, and control.
The NetFPGA-1G-CML board.
The NetFPGA-1G-CML is designed to support the Stanford NetFPGA architecture with reference designs available
through the NetFPGA GitHub Organization (www.github.com/organizations/NetFPGA). It is fully compatible with
Xilinx Vivado™ and ISE® Design Suites as well as Xilinx SDK for embedded software design.
DOC#: 6015-502-001
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Xilinx Kintex-7 XC7K325T-1FFG676 FPGA
Low-jitter 200 MHz oscillator
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Four 10/100/1000 Ethernet PHYs with
RGMII
X4 Gen 2 PCI Express
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X16 4.5 MB QDRII+ static RAM (450 MHz)
X8 512 MB DDR3 dynamic RAM (800 MHz)
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1-Gbit BPI Flash
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SD card slot
32-bit PIC microcontroller
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USB microcontroller
Real time clock
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Crypto-authentication chip
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High pin count FMC connector (VITA 57)
withh 100 Select-IO and 4 GTX serial pairs
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Two Pmod connectors
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Four on-board LEDs and four on-board
general-purpose buttons
1300 Henley Court
Pullman, WA 99163
509.334.6306
www.digilentinc.com
Page 1 of 21
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Related Manuals for Digilent NetFPGA-1G-CML
Summary of Contents for Digilent NetFPGA-1G-CML
- Page 1 This manual applies to the NetFPGA-1G-CML rev. E Overview The NetFPGA-1G-CML is a versatile, low-cost network hardware development platform featuring a Xilinx® Kintex®- 7 XC7K325T FPGA and includes four Ethernet interfaces capable of negotiating up to 1 GB/s connections. 512 MB of 800 MHz DDR3 can support high-throughput packet buffering while 4.5 MB of QDRII+ can maintain low-latency...
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Page 2: Fpga Configuration
Digilent's Adept and Xilinx's iMPACT applications can directly program the FPGA using a .bit file a standard USB A to Micro B cable connected to J12 or through any of several Digilent JTAG programming cables connected to J15. -
Page 3: Power Supplies
The PIC can also measure USB current and voltage by accessing the on-chip power monitor via the PIC I2C peripheral bus. Copyright Digilent, Inc. All rights reserved. Page 3 of 21... -
Page 4: Oscillators And Clocks
1.78 MB of on-chip, error-corrected static RAM that can be used for a variety of purposes ranging from program storage for deeply embedded "bare metal" applications to data Copyright Digilent, Inc. All rights reserved. Page 4 of 21... -
Page 5: Ddr3 Memory
Select I/O within the design. As a result, non-volatile data of any type can also be stored to and retrieved from the BPI after device configuration is complete. More information regarding BPI based device configuration is Copyright Digilent, Inc. All rights reserved. Page 5 of 21... -
Page 6: Pcie Interface
This provides a significant reduction in the number of FPGA I/O pins required to support the four Ethernet interfaces. Copyright Digilent, Inc. All rights reserved. Page 6 of 21 Other product and company names mentioned may be trademarks of their respective owners. - Page 7 To program the PIC device, connect a PICkit 3 to the NetFPGA-1G by placing a 1x6 pin header in the zig-zag connector J14 and connect it to the PICkit 3 using a 6-pin cable. If Digilent's 6-pin Pmod cable is used, the white indicator dot on the NetFPGA-1G side should be above pin 6, and the dot on the PICkit 3 side will be face-up and opposite the white arrow on the PICkit 3.
- Page 8 LED IO port constraints. 13 Pmod Expansion Connectors The NetFPGA-1G has two 12-pin connectors to support I/O expansion via Digilent Pmods. Digilent manufactures Pmod accessories that support a large variety of external interfaces that increase system flexibility. The Pmod connectors are 2x6 right-angle 100-mil female connectors that work with the standard 2x6 headers available from a variety of distributors.
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Page 9: Expansion Connector
FMC module and carrier requirements. Refer to Appendix B for specific I/O constraints relating FPGA pins to their associated FMC control and connector pins. Copyright Digilent, Inc. All rights reserved. Page 9 of 21 Other product and company names mentioned may be trademarks of their respective owners. -
Page 10: Appendix A: Manufacturing Test
Many tests can be run independently without the need for additional hardware. For example, the HiTech Global Breakout Board is only needed to test the PCIe edge connector. More details regarding individual tests are provided in the NetFPGA-1G Manufacturing Test Reference Manual available on the Digilent web site. Copyright Digilent, Inc. All rights reserved. -
Page 11: Appendix B: Fpga Pin Constraints
IOSTANDARD = SSTL15; NET ddr3_addr[1] LOC = Y2 IOSTANDARD = SSTL15; NET ddr3_addr[2] LOC = W3 IOSTANDARD = SSTL15; Copyright Digilent, Inc. All rights reserved. Page 11 of 21 Other product and company names mentioned may be trademarks of their respective owners. - Page 12 IOSTANDARD = HSTL_I; NET qdriip_d[1] LOC = V7 IOSTANDARD = HSTL_I; NET qdriip_d[2] LOC = W9 IOSTANDARD = HSTL_I; Copyright Digilent, Inc. All rights reserved. Page 12 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 13 IOSTANDARD = HSTL_I; NET qdriip_sa[16] LOC = AA12 IOSTANDARD = HSTL_I; NET qdriip_sa[17] LOC = AA10 IOSTANDARD = HSTL_I; Copyright Digilent, Inc. All rights reserved. Page 13 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 14 IOSTANDARD = LVCMOS33; NET bpi_data<0> LOC = B24 IOSTANDARD = LVCMOS33; NET bpi_data<1> LOC = A25 IOSTANDARD = LVCMOS33; Copyright Digilent, Inc. All rights reserved. Page 14 of 21 Other product and company names mentioned may be trademarks of their respective owners.
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Page 15: Sd Card Connector
IOSTANDARD = LVCMOS18; NET sd-d2 LOC = AD15 IOSTANDARD = LVCMOS18; NET sd-d3 LOC = AE18 IOSTANDARD = LVCMOS18; Copyright Digilent, Inc. All rights reserved. Page 15 of 21 Other product and company names mentioned may be trademarks of their respective owners. -
Page 16: Pci Express
IOSTANDARD = LVCMOS18; NET rgmii_rxd_1[1] LOC = B14 IOSTANDARD = LVCMOS18; NET rgmii_rxd_1[2] LOC = E12 IOSTANDARD = LVCMOS18; Copyright Digilent, Inc. All rights reserved. Page 16 of 21 Other product and company names mentioned may be trademarks of their respective owners. - Page 17 IOSTANDARD = LVCMOS18; NET pic2fpga_sdo LOC = V16 IOSTANDARD = LVCMOS18; NET pic2fpga_ss_n LOC = W16 IOSTANDARD = LVCMOS18; Copyright Digilent, Inc. All rights reserved. Page 17 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 18 LOC = AF19 IOSTANDARD = LVCMOS18; NET SET_VADJ2 LOC = AF20 IOSTANDARD = LVCMOS18; NET FMC_LA00_P LOC = Y22; Copyright Digilent, Inc. All rights reserved. Page 18 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 19 LOC = T17; NET FMC_LA25_P LOC = T18; NET FMC_LA25_N LOC = T19; NET FMC_LA26_P LOC = M21; Copyright Digilent, Inc. All rights reserved. Page 19 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 20 LOC = A3; NET FMC_DP0_C2M_P LOC = A4; NET FMC_DP1_M2C_N LOC = E3; NET FMC_DP1_M2C_P LOC = E4; Copyright Digilent, Inc. All rights reserved. Page 20 of 21 Other product and company names mentioned may be trademarks of their respective owners.
- Page 21 LOC = F5; NET FMC_GBTCLK0_M2C_P LOC = F6; NET FMC_GBTCLK1_M2C_N LOC = D5; NET FMC_GBTCLK1_M2C_P LOC = D6; Copyright Digilent, Inc. All rights reserved. Page 21 of 21 Other product and company names mentioned may be trademarks of their respective owners.
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